Jeremy Janella
1488 lines
90 KiB
Devicetree
1488 lines
90 KiB
Devicetree
/dts-v1/;
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/* node '/' defined in zephyr/dts/common/skeleton.dtsi:9 */
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/ {
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#address-cells = < 0x1 >; /* in zephyr/dts/common/skeleton.dtsi:10 */
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#size-cells = < 0x1 >; /* in zephyr/dts/common/skeleton.dtsi:11 */
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model = "STMicroelectronics STM32G431RB-NUCLEO board"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:15 */
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compatible = "st,stm32g431rb-nucleo"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:16 */
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/* node '/chosen' defined in zephyr/dts/common/skeleton.dtsi:13 */
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chosen {
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zephyr,crc = &crc; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:26 */
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zephyr,entropy = &rng; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:27 */
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zephyr,flash-controller = &flash; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:28 */
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zephyr,console = &lpuart1; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:19 */
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zephyr,shell-uart = &lpuart1; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:20 */
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zephyr,sram = &sram0; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:21 */
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zephyr,flash = &flash0; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:22 */
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zephyr,code-partition = &boot_partition; /* in bootloader/mcuboot/boot/zephyr/app.overlay:3 */
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};
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/* node '/aliases' defined in zephyr/dts/common/skeleton.dtsi:15 */
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aliases {
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led0 = &green_led; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:54 */
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mcuboot-led0 = &green_led; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:55 */
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pwm-led0 = &green_pwm_led; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:56 */
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sw0 = &user_button; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:57 */
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watchdog0 = &iwdg; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:58 */
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};
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/* node '/soc' defined in zephyr/dts/arm/armv7-m.dtsi:6 */
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soc {
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#address-cells = < 0x1 >; /* in zephyr/dts/arm/armv7-m.dtsi:7 */
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#size-cells = < 0x1 >; /* in zephyr/dts/arm/armv7-m.dtsi:8 */
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interrupt-parent = < &nvic >; /* in zephyr/dts/arm/armv7-m.dtsi:10 */
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ranges; /* in zephyr/dts/arm/armv7-m.dtsi:11 */
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compatible = "st,stm32g431",
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"st,stm32g4",
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"simple-bus"; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:11 */
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/* node '/soc/interrupt-controller@e000e100' defined in zephyr/dts/arm/armv7-m.dtsi:13 */
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nvic: interrupt-controller@e000e100 {
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#address-cells = < 0x1 >; /* in zephyr/dts/arm/armv7-m.dtsi:14 */
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compatible = "arm,v7m-nvic"; /* in zephyr/dts/arm/armv7-m.dtsi:15 */
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reg = < 0xe000e100 0xc00 >; /* in zephyr/dts/arm/armv7-m.dtsi:16 */
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interrupt-controller; /* in zephyr/dts/arm/armv7-m.dtsi:17 */
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#interrupt-cells = < 0x2 >; /* in zephyr/dts/arm/armv7-m.dtsi:18 */
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arm,num-irq-priority-bits = < 0x4 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:927 */
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phandle = < 0x1 >; /* in zephyr/dts/arm/armv7-m.dtsi:10 */
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};
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/* node '/soc/timer@e000e010' defined in zephyr/dts/arm/armv7-m.dtsi:21 */
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systick: timer@e000e010 {
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compatible = "arm,armv7m-systick"; /* in zephyr/dts/arm/armv7-m.dtsi:22 */
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reg = < 0xe000e010 0x10 >; /* in zephyr/dts/arm/armv7-m.dtsi:23 */
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};
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/* node '/soc/adc@50000000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:111 */
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adc1: adc@50000000 {
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compatible = "st,stm32-adc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:112 */
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reg = < 0x50000000 0x100 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:113 */
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clocks = < &rcc 0x4c 0x2000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:114 */
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clock-names = "adcx"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:115 */
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interrupts = < 0x12 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:116 */
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#io-channel-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:117 */
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st,adc-resolutions = < 0xc 0xa 0x8 0x6 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:118 */
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sampling-times = < 0x3 0x7 0xd 0x19 0x30 0x5d 0xf8 0x281 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:119 */
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st,adc-sequencer = "programmable"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:120 */
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st,adc-oversampler = "minimal"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:121 */
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st,adc-internal-regulator = "startup-sw-delay"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:122 */
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st,adc-has-deep-powerdown; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:123 */
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st,adc-has-differential-support; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:124 */
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st,adc-has-injected-support; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:125 */
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status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:126 */
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phandle = < 0x20 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:877 */
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};
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/* node '/soc/adc@50000100' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:129 */
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adc2: adc@50000100 {
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compatible = "st,stm32-adc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:130 */
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reg = < 0x50000100 0x100 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:131 */
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clocks = < &rcc 0x4c 0x2000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:132 */
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clock-names = "adcx"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:133 */
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interrupts = < 0x12 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:134 */
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#io-channel-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:135 */
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st,adc-resolutions = < 0xc 0xa 0x8 0x6 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:136 */
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sampling-times = < 0x3 0x7 0xd 0x19 0x30 0x5d 0xf8 0x281 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:137 */
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st,adc-sequencer = "programmable"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:138 */
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st,adc-oversampler = "minimal"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:139 */
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st,adc-internal-regulator = "startup-sw-delay"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:140 */
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st,adc-has-deep-powerdown; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:141 */
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st,adc-has-differential-support; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:142 */
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st,adc-has-injected-support; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:143 */
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status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:144 */
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};
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/* node '/soc/dac@50000800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:147 */
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dac1: dac@50000800 {
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compatible = "st,stm32-dac"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:148 */
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reg = < 0x50000800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:149 */
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clocks = < &rcc 0x4c 0x10000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:150 */
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#io-channel-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:152 */
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status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:205 */
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pinctrl-0 = < &dac1_out1_pa4 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:206 */
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pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:207 */
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};
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/* node '/soc/dac@50001000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:155 */
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dac3: dac@50001000 {
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compatible = "st,stm32-dac"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:156 */
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reg = < 0x50001000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:157 */
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clocks = < &rcc 0x4c 0x40000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:158 */
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status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:159 */
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#io-channel-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:160 */
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};
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/* node '/soc/flash-controller@40022000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:163 */
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller",
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"st,stm32g4-flash-controller"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:164 */
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reg = < 0x40022000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:165 */
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interrupts = < 0x3 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:166 */
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clocks = < &rcc 0x48 0x100 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:167 */
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#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:169 */
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#size-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:170 */
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ranges; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:171 */
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/* node '/soc/flash-controller@40022000/flash@8000000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:173 */
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash",
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"soc-nv-flash"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:174 */
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#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:175 */
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#size-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:176 */
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write-block-size = < 0x8 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:177 */
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erase-block-size = < 0x800 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:178 */
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max-erase-time = < 0x19 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:180 */
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reg = < 0x8000000 0x20000 >; /* in zephyr/dts/arm/st/g4/stm32g431Xb.dtsi:14 */
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ranges = < 0x0 0x8000000 0x20000 >; /* in zephyr/dts/arm/st/g4/stm32g431Xb.dtsi:15 */
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/* node '/soc/flash-controller@40022000/flash@8000000/partitions' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:168 */
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partitions {
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#address-cells = < 0x1 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:169 */
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#size-cells = < 0x1 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:170 */
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ranges; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:171 */
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/* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@0' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:173 */
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boot_partition: partition@0 {
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compatible = "zephyr,mapped-partition"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:174 */
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label = "mcuboot"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:175 */
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reg = < 0x0 0x8800 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:176 */
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};
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/* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@8800' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:179 */
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slot0_partition: partition@8800 {
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compatible = "zephyr,mapped-partition"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:180 */
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label = "image-0"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:181 */
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reg = < 0x8800 0xc000 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:182 */
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};
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/* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@14800' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:185 */
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slot1_partition: partition@14800 {
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compatible = "zephyr,mapped-partition"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:186 */
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label = "image-1"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:187 */
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reg = < 0x14800 0xa800 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:188 */
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};
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/* node '/soc/flash-controller@40022000/flash@8000000/partitions/partition@1f000' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:192 */
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storage_partition: partition@1f000 {
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compatible = "zephyr,mapped-partition"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:193 */
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label = "storage"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:194 */
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reg = < 0x1f000 0x1000 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:195 */
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};
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};
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};
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/* node '/soc/flash-controller@40022000/flash@1fff7000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:183 */
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st_nvm_user_otp: flash@1fff7000 {
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compatible = "st,stm32-nvm-otp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:184 */
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reg = < 0x1fff7000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:185 */
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status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:186 */
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};
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/* node '/soc/flash-controller@40022000/flash@1fff7500' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:190 */
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flash@1fff7500 {
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compatible = "st,stm32-nvm-otp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:191 */
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reg = < 0x1fff7500 0x300 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:192 */
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/* node '/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:194 */
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nvmem-layout {
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compatible = "fixed-layout"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:195 */
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#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:196 */
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#size-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:197 */
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/* node '/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal1@a8' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:199 */
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ts_cal1_otp: ts-cal1@a8 {
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reg = < 0xa8 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:200 */
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#nvmem-cell-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:201 */
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read-only; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:202 */
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phandle = < 0x1e >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:872 */
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};
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/* node '/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/vrefint@aa' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:205 */
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vrefint_otp: vrefint@aa {
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reg = < 0xaa 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:206 */
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#nvmem-cell-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:207 */
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read-only; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:208 */
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phandle = < 0x21 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:883 */
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};
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/* node '/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal2@ca' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:211 */
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ts_cal2_otp: ts-cal2@ca {
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reg = < 0xca 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:212 */
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#nvmem-cell-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:213 */
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read-only; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:214 */
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phandle = < 0x1f >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:872 */
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};
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};
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};
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};
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/* node '/soc/rcc@40021000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:220 */
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:221 */
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#clock-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:222 */
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reg = < 0x40021000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:223 */
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undershoot-prevention; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:224 */
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clocks = < &pll >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:90 */
|
|
clock-frequency = < 0xa21fe80 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:91 */
|
|
ahb-prescaler = < 0x1 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:92 */
|
|
apb1-prescaler = < 0x1 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:93 */
|
|
apb2-prescaler = < 0x1 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:94 */
|
|
phandle = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:114 */
|
|
|
|
/* node '/soc/rcc@40021000/reset-controller' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:226 */
|
|
rctl: reset-controller {
|
|
compatible = "st,stm32-rcc-rctl"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:227 */
|
|
#reset-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:228 */
|
|
phandle = < 0x5 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:315 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/interrupt-controller@40010400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:232 */
|
|
exti: interrupt-controller@40010400 {
|
|
compatible = "st,stm32-exti"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:233 */
|
|
interrupt-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:234 */
|
|
#interrupt-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:235 */
|
|
#address-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:236 */
|
|
reg = < 0x40010400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:237 */
|
|
clocks = < &rcc 0x60 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:238 */
|
|
num-lines = < 0x40 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:239 */
|
|
interrupts = < 0x6 0x0 >,
|
|
< 0x7 0x0 >,
|
|
< 0x8 0x0 >,
|
|
< 0x9 0x0 >,
|
|
< 0xa 0x0 >,
|
|
< 0x17 0x0 >,
|
|
< 0x28 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:240 */
|
|
interrupt-names = "line0",
|
|
"line1",
|
|
"line2-TSC",
|
|
"line3",
|
|
"line4",
|
|
"line5-9",
|
|
"line10-15"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:242 */
|
|
line-ranges = < 0x0 0x1 >,
|
|
< 0x1 0x1 >,
|
|
< 0x2 0x1 >,
|
|
< 0x3 0x1 >,
|
|
< 0x4 0x1 >,
|
|
< 0x5 0x5 >,
|
|
< 0xa 0x6 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:244 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:248 */
|
|
pinctrl: pin-controller@48000000 {
|
|
compatible = "st,stm32-pinctrl"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:249 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:250 */
|
|
#size-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:251 */
|
|
reg = < 0x48000000 0x2000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:252 */
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48000000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:254 */
|
|
gpioa: gpio@48000000 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:255 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:256 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:257 */
|
|
reg = < 0x48000000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:258 */
|
|
clocks = < &rcc 0x4c 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:259 */
|
|
phandle = < 0x25 >; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:15 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48000400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:262 */
|
|
gpiob: gpio@48000400 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:263 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:264 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:265 */
|
|
reg = < 0x48000400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:266 */
|
|
clocks = < &rcc 0x4c 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:267 */
|
|
phandle = < 0xf >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:126 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48000800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:270 */
|
|
gpioc: gpio@48000800 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:271 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:272 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:273 */
|
|
reg = < 0x48000800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:274 */
|
|
clocks = < &rcc 0x4c 0x4 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:275 */
|
|
phandle = < 0x26 >; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:15 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48000c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:278 */
|
|
gpiod: gpio@48000c00 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:279 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:280 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:281 */
|
|
reg = < 0x48000c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:282 */
|
|
clocks = < &rcc 0x4c 0x8 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:283 */
|
|
phandle = < 0x27 >; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:15 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48001000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:286 */
|
|
gpioe: gpio@48001000 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:287 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:288 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:289 */
|
|
reg = < 0x48001000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:290 */
|
|
clocks = < &rcc 0x4c 0x10 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:291 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48001400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:294 */
|
|
gpiof: gpio@48001400 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:295 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:296 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:297 */
|
|
reg = < 0x48001400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:298 */
|
|
clocks = < &rcc 0x4c 0x20 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:299 */
|
|
phandle = < 0x28 >; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:15 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/gpio@48001800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:302 */
|
|
gpiog: gpio@48001800 {
|
|
compatible = "st,stm32-gpio"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:303 */
|
|
gpio-controller; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:304 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:305 */
|
|
reg = < 0x48001800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:306 */
|
|
clocks = < &rcc 0x4c 0x40 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:307 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/dac1_out1_pa4' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:461 */
|
|
dac1_out1_pa4: dac1_out1_pa4 {
|
|
pinmux = < 0x90 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:462 */
|
|
phandle = < 0x3 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:206 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/i2c1_scl_pb8' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:503 */
|
|
i2c1_scl_pb8: i2c1_scl_pb8 {
|
|
pinmux = < 0x304 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:504 */
|
|
bias-pull-up; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:505 */
|
|
drive-open-drain; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:506 */
|
|
phandle = < 0xa >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:118 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/i2c1_sda_pb9' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:547 */
|
|
i2c1_sda_pb9: i2c1_sda_pb9 {
|
|
pinmux = < 0x324 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:548 */
|
|
bias-pull-up; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:549 */
|
|
drive-open-drain; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:550 */
|
|
phandle = < 0xb >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:118 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi1_miso_pa6' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:932 */
|
|
spi1_miso_pa6: spi1_miso_pa6 {
|
|
pinmux = < 0xc5 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:933 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:934 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:935 */
|
|
phandle = < 0xd >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:124 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi2_miso_pb14' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:950 */
|
|
spi2_miso_pb14: spi2_miso_pb14 {
|
|
pinmux = < 0x3c5 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:951 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:952 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:953 */
|
|
phandle = < 0x12 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:131 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi3_miso_pc11' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:962 */
|
|
spi3_miso_pc11: spi3_miso_pc11 {
|
|
pinmux = < 0x566 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:963 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:964 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:965 */
|
|
phandle = < 0x16 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:139 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi1_mosi_pa7' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:970 */
|
|
spi1_mosi_pa7: spi1_mosi_pa7 {
|
|
pinmux = < 0xe5 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:971 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:972 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:973 */
|
|
phandle = < 0xe >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:124 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi2_mosi_pb15' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:988 */
|
|
spi2_mosi_pb15: spi2_mosi_pb15 {
|
|
pinmux = < 0x3e5 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:989 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:990 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:991 */
|
|
phandle = < 0x13 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:131 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi3_mosi_pc12' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1000 */
|
|
spi3_mosi_pc12: spi3_mosi_pc12 {
|
|
pinmux = < 0x586 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1001 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1002 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1003 */
|
|
phandle = < 0x17 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:139 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi2_nss_pb12' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1020 */
|
|
spi2_nss_pb12: spi2_nss_pb12 {
|
|
pinmux = < 0x385 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1021 */
|
|
bias-pull-up; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1022 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1023 */
|
|
phandle = < 0x10 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:131 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi3_nss_pa15' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1038 */
|
|
spi3_nss_pa15: spi3_nss_pa15 {
|
|
pinmux = < 0x1e6 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1039 */
|
|
bias-pull-up; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1040 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1041 */
|
|
phandle = < 0x14 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:139 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi1_sck_pa5' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1046 */
|
|
spi1_sck_pa5: spi1_sck_pa5 {
|
|
pinmux = < 0xa5 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1047 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1048 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1049 */
|
|
phandle = < 0xc >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:124 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi2_sck_pb13' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1058 */
|
|
spi2_sck_pb13: spi2_sck_pb13 {
|
|
pinmux = < 0x3a5 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1059 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1060 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1061 */
|
|
phandle = < 0x11 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:131 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/spi3_sck_pc10' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1076 */
|
|
spi3_sck_pc10: spi3_sck_pc10 {
|
|
pinmux = < 0x546 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1077 */
|
|
bias-pull-down; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1078 */
|
|
slew-rate = "very-high-speed"; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1079 */
|
|
phandle = < 0x15 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:139 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/tim2_ch1_pa5' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1266 */
|
|
tim2_ch1_pa5: tim2_ch1_pa5 {
|
|
pinmux = < 0xa1 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1267 */
|
|
phandle = < 0x18 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:150 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/lpuart1_rx_pa3' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1613 */
|
|
lpuart1_rx_pa3: lpuart1_rx_pa3 {
|
|
pinmux = < 0x6c >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1614 */
|
|
phandle = < 0x9 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:111 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/usart1_rx_pc5' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1633 */
|
|
usart1_rx_pc5: usart1_rx_pc5 {
|
|
pinmux = < 0x4a7 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1634 */
|
|
phandle = < 0x7 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:104 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/lpuart1_tx_pa2' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1667 */
|
|
lpuart1_tx_pa2: lpuart1_tx_pa2 {
|
|
pinmux = < 0x4c >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1668 */
|
|
bias-pull-up; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1669 */
|
|
phandle = < 0x8 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:111 */
|
|
};
|
|
|
|
/* node '/soc/pin-controller@48000000/usart1_tx_pc4' defined in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1692 */
|
|
usart1_tx_pc4: usart1_tx_pc4 {
|
|
pinmux = < 0x487 >; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1693 */
|
|
bias-pull-up; /* in modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi:1694 */
|
|
phandle = < 0x6 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:104 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/serial@40013800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:311 */
|
|
usart1: arduino_serial: serial@40013800 {
|
|
compatible = "st,stm32-usart",
|
|
"st,stm32-uart"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:312 */
|
|
reg = < 0x40013800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:313 */
|
|
clocks = < &rcc 0x60 0x4000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:314 */
|
|
resets = < &rctl 0x80e >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:315 */
|
|
interrupts = < 0x25 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:316 */
|
|
pinctrl-0 = < &usart1_tx_pc4 &usart1_rx_pc5 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:104 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:105 */
|
|
current-speed = < 0x1c200 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:106 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:107 */
|
|
};
|
|
|
|
/* node '/soc/serial@40004400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:320 */
|
|
usart2: serial@40004400 {
|
|
compatible = "st,stm32-usart",
|
|
"st,stm32-uart"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:321 */
|
|
reg = < 0x40004400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:322 */
|
|
clocks = < &rcc 0x58 0x20000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:323 */
|
|
resets = < &rctl 0x711 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:324 */
|
|
interrupts = < 0x26 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:325 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:326 */
|
|
};
|
|
|
|
/* node '/soc/serial@40004800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:329 */
|
|
usart3: serial@40004800 {
|
|
compatible = "st,stm32-usart",
|
|
"st,stm32-uart"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:330 */
|
|
reg = < 0x40004800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:331 */
|
|
clocks = < &rcc 0x58 0x40000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:332 */
|
|
resets = < &rctl 0x712 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:333 */
|
|
interrupts = < 0x27 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:334 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:335 */
|
|
};
|
|
|
|
/* node '/soc/serial@40004c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:338 */
|
|
uart4: serial@40004c00 {
|
|
compatible = "st,stm32-uart"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:339 */
|
|
reg = < 0x40004c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:340 */
|
|
clocks = < &rcc 0x58 0x80000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:341 */
|
|
resets = < &rctl 0x713 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:342 */
|
|
interrupts = < 0x34 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:343 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:344 */
|
|
};
|
|
|
|
/* node '/soc/serial@40008000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:347 */
|
|
lpuart1: serial@40008000 {
|
|
compatible = "st,stm32-lpuart",
|
|
"st,stm32-uart"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:348 */
|
|
reg = < 0x40008000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:349 */
|
|
clocks = < &rcc 0x5c 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:350 */
|
|
resets = < &rctl 0x780 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:351 */
|
|
interrupts = < 0x5b 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:352 */
|
|
pinctrl-0 = < &lpuart1_tx_pa2 &lpuart1_rx_pa3 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:111 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:112 */
|
|
current-speed = < 0x1c200 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:113 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:114 */
|
|
};
|
|
|
|
/* node '/soc/watchdog@40003000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:356 */
|
|
iwdg: watchdog@40003000 {
|
|
compatible = "st,stm32-watchdog"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:357 */
|
|
reg = < 0x40003000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:358 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:201 */
|
|
};
|
|
|
|
/* node '/soc/watchdog@40002c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:362 */
|
|
wwdg: watchdog@40002c00 {
|
|
compatible = "st,stm32-window-watchdog"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:363 */
|
|
reg = < 0x40002c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:364 */
|
|
clocks = < &rcc 0x58 0x800 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:365 */
|
|
interrupts = < 0x0 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:366 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:367 */
|
|
};
|
|
|
|
/* node '/soc/i2c@40005400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:370 */
|
|
i2c1: arduino_i2c: i2c@40005400 {
|
|
compatible = "st,stm32-i2c-v2"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:371 */
|
|
clock-frequency = < 0x186a0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:372 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:373 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:374 */
|
|
reg = < 0x40005400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:375 */
|
|
clocks = < &rcc 0x58 0x200000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:376 */
|
|
interrupts = < 0x1f 0x0 >,
|
|
< 0x20 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:377 */
|
|
interrupt-names = "event",
|
|
"error"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:378 */
|
|
pinctrl-0 = < &i2c1_scl_pb8 &i2c1_sda_pb9 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:118 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:119 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:120 */
|
|
phandle = < 0x22 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:905 */
|
|
};
|
|
|
|
/* node '/soc/i2c@40005800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:382 */
|
|
i2c2: i2c@40005800 {
|
|
compatible = "st,stm32-i2c-v2"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:383 */
|
|
clock-frequency = < 0x186a0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:384 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:385 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:386 */
|
|
reg = < 0x40005800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:387 */
|
|
clocks = < &rcc 0x58 0x400000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:388 */
|
|
interrupts = < 0x21 0x0 >,
|
|
< 0x22 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:389 */
|
|
interrupt-names = "event",
|
|
"error"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:390 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:391 */
|
|
phandle = < 0x23 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:913 */
|
|
};
|
|
|
|
/* node '/soc/i2c@40007800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:394 */
|
|
i2c3: i2c@40007800 {
|
|
compatible = "st,stm32-i2c-v2"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:395 */
|
|
clock-frequency = < 0x186a0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:396 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:397 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:398 */
|
|
reg = < 0x40007800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:399 */
|
|
clocks = < &rcc 0x58 0x40000000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:400 */
|
|
interrupts = < 0x5c 0x0 >,
|
|
< 0x5d 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:401 */
|
|
interrupt-names = "event",
|
|
"error"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:402 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:403 */
|
|
phandle = < 0x24 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:921 */
|
|
};
|
|
|
|
/* node '/soc/spi@40013000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:406 */
|
|
spi1: arduino_spi: spi@40013000 {
|
|
compatible = "st,stm32-spi-fifo",
|
|
"st,stm32-spi"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:407 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:408 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:409 */
|
|
reg = < 0x40013000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:410 */
|
|
interrupts = < 0x23 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:411 */
|
|
clocks = < &rcc 0x60 0x1000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:412 */
|
|
st,spi-data-width = "full-4-to-16-bit"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:413 */
|
|
pinctrl-0 = < &spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:124 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:125 */
|
|
cs-gpios = < &gpiob 0x6 0x11 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:126 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:127 */
|
|
};
|
|
|
|
/* node '/soc/spi@40003800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:417 */
|
|
spi2: spi@40003800 {
|
|
compatible = "st,stm32-spi-fifo",
|
|
"st,stm32-spi"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:418 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:419 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:420 */
|
|
reg = < 0x40003800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:421 */
|
|
clocks = < &rcc 0x58 0x4000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:422 */
|
|
interrupts = < 0x24 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:423 */
|
|
st,spi-data-width = "full-4-to-16-bit"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:424 */
|
|
pinctrl-0 = < &spi2_nss_pb12 &spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:131 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:133 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:134 */
|
|
};
|
|
|
|
/* node '/soc/spi@40003c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:428 */
|
|
spi3: spi@40003c00 {
|
|
compatible = "st,stm32-spi-fifo",
|
|
"st,stm32-spi"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:429 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:430 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:431 */
|
|
reg = < 0x40003c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:432 */
|
|
clocks = < &rcc 0x58 0x8000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:433 */
|
|
interrupts = < 0x33 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:434 */
|
|
st,spi-data-width = "full-4-to-16-bit"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:435 */
|
|
pinctrl-0 = < &spi3_nss_pa15 &spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:139 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:141 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:142 */
|
|
};
|
|
|
|
/* node '/soc/can@40006400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:439 */
|
|
fdcan1: can@40006400 {
|
|
compatible = "st,stm32-fdcan"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:440 */
|
|
reg = < 0x40006400 0x400 >,
|
|
< 0x4000a400 0x350 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:441 */
|
|
reg-names = "m_can",
|
|
"message_ram"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:442 */
|
|
interrupts = < 0x15 0x0 >,
|
|
< 0x16 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:443 */
|
|
interrupt-names = "int0",
|
|
"int1"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:444 */
|
|
clocks = < &rcc 0x58 0x2000000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:445 */
|
|
bosch,mram-cfg = < 0x0 0x1c 0x8 0x3 0x3 0x0 0x3 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:446 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:447 */
|
|
};
|
|
|
|
/* node '/soc/timers@40007c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:450 */
|
|
lptim1: stm32_lp_tick_source: timers@40007c00 {
|
|
compatible = "st,stm32-lptim"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:451 */
|
|
resets = < &rctl 0x71f >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:453 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:454 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:455 */
|
|
reg = < 0x40007c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:456 */
|
|
interrupts = < 0x31 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:457 */
|
|
interrupt-names = "wakeup"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:458 */
|
|
clocks = < &rcc 0x58 0x80000000 >,
|
|
< &rcc 0x2 0x3320088 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:156 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:158 */
|
|
};
|
|
|
|
/* node '/soc/timers@40012c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:462 */
|
|
timers1: timers@40012c00 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:463 */
|
|
reg = < 0x40012c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:464 */
|
|
clocks = < &rcc 0x60 0x800 >,
|
|
< &rcc 0xa 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:465 */
|
|
resets = < &rctl 0x80b >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:467 */
|
|
interrupts = < 0x18 0x0 >,
|
|
< 0x19 0x0 >,
|
|
< 0x1a 0x0 >,
|
|
< 0x1b 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:468 */
|
|
interrupt-names = "brk",
|
|
"up",
|
|
"trgcom",
|
|
"cc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:469 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:470 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:471 */
|
|
|
|
/* node '/soc/timers@40012c00/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:473 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:474 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:475 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:476 */
|
|
};
|
|
|
|
/* node '/soc/timers@40012c00/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:479 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:480 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:481 */
|
|
};
|
|
|
|
/* node '/soc/timers@40012c00/qdec' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:484 */
|
|
qdec {
|
|
compatible = "st,stm32-qdec"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:485 */
|
|
st,input-filter-level = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:486 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:487 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40000000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:491 */
|
|
timers2: timers@40000000 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:492 */
|
|
reg = < 0x40000000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:493 */
|
|
clocks = < &rcc 0x58 0x1 >,
|
|
< &rcc 0x9 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:494 */
|
|
resets = < &rctl 0x700 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:496 */
|
|
interrupts = < 0x1c 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:497 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:498 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:499 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:146 */
|
|
|
|
/* node '/soc/timers@40000000/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:502 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:503 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:504 */
|
|
};
|
|
|
|
/* node '/soc/timers@40000000/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:507 */
|
|
pwm2: pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:508 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:510 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:149 */
|
|
pinctrl-0 = < &tim2_ch1_pa5 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:150 */
|
|
pinctrl-names = "default"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:151 */
|
|
phandle = < 0x29 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:39 */
|
|
};
|
|
|
|
/* node '/soc/timers@40000000/qdec' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:513 */
|
|
qdec {
|
|
compatible = "st,stm32-qdec"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:514 */
|
|
st,input-filter-level = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:515 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:516 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40000400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:520 */
|
|
timers3: timers@40000400 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:521 */
|
|
reg = < 0x40000400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:522 */
|
|
clocks = < &rcc 0x58 0x2 >,
|
|
< &rcc 0x9 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:523 */
|
|
resets = < &rctl 0x701 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:525 */
|
|
interrupts = < 0x1d 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:526 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:527 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:528 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:529 */
|
|
|
|
/* node '/soc/timers@40000400/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:531 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:532 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:533 */
|
|
};
|
|
|
|
/* node '/soc/timers@40000400/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:536 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:537 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:538 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:539 */
|
|
};
|
|
|
|
/* node '/soc/timers@40000400/qdec' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:542 */
|
|
qdec {
|
|
compatible = "st,stm32-qdec"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:543 */
|
|
st,input-filter-level = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:544 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:545 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40000800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:549 */
|
|
timers4: timers@40000800 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:550 */
|
|
reg = < 0x40000800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:551 */
|
|
clocks = < &rcc 0x58 0x4 >,
|
|
< &rcc 0x9 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:552 */
|
|
resets = < &rctl 0x702 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:554 */
|
|
interrupts = < 0x1e 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:555 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:556 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:557 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:558 */
|
|
|
|
/* node '/soc/timers@40000800/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:560 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:561 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:562 */
|
|
};
|
|
|
|
/* node '/soc/timers@40000800/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:565 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:566 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:567 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:568 */
|
|
};
|
|
|
|
/* node '/soc/timers@40000800/qdec' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:571 */
|
|
qdec {
|
|
compatible = "st,stm32-qdec"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:572 */
|
|
st,input-filter-level = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:573 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:574 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40001000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:578 */
|
|
timers6: timers@40001000 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:579 */
|
|
reg = < 0x40001000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:580 */
|
|
clocks = < &rcc 0x58 0x10 >,
|
|
< &rcc 0x9 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:581 */
|
|
resets = < &rctl 0x704 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:583 */
|
|
interrupts = < 0x36 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:584 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:585 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:586 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:587 */
|
|
|
|
/* node '/soc/timers@40001000/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:589 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:590 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:591 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40001400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:595 */
|
|
timers7: timers@40001400 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:596 */
|
|
reg = < 0x40001400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:597 */
|
|
clocks = < &rcc 0x58 0x20 >,
|
|
< &rcc 0x9 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:598 */
|
|
resets = < &rctl 0x705 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:600 */
|
|
interrupts = < 0x37 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:601 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:602 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:603 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:604 */
|
|
|
|
/* node '/soc/timers@40001400/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:606 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:607 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:608 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40013400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:612 */
|
|
timers8: timers@40013400 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:613 */
|
|
reg = < 0x40013400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:614 */
|
|
clocks = < &rcc 0x60 0x2000 >,
|
|
< &rcc 0xa 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:615 */
|
|
resets = < &rctl 0x80d >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:617 */
|
|
interrupts = < 0x2b 0x0 >,
|
|
< 0x2c 0x0 >,
|
|
< 0x2d 0x0 >,
|
|
< 0x2e 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:618 */
|
|
interrupt-names = "brk",
|
|
"up",
|
|
"trgcom",
|
|
"cc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:619 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:620 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:621 */
|
|
|
|
/* node '/soc/timers@40013400/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:623 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:624 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:625 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:626 */
|
|
};
|
|
|
|
/* node '/soc/timers@40013400/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:629 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:630 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:631 */
|
|
};
|
|
|
|
/* node '/soc/timers@40013400/qdec' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:634 */
|
|
qdec {
|
|
compatible = "st,stm32-qdec"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:635 */
|
|
st,input-filter-level = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:636 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:637 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40014000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:641 */
|
|
timers15: timers@40014000 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:642 */
|
|
reg = < 0x40014000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:643 */
|
|
clocks = < &rcc 0x60 0x10000 >,
|
|
< &rcc 0xa 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:644 */
|
|
resets = < &rctl 0x810 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:646 */
|
|
interrupts = < 0x18 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:647 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:648 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:649 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:650 */
|
|
|
|
/* node '/soc/timers@40014000/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:652 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:653 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:654 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:655 */
|
|
};
|
|
|
|
/* node '/soc/timers@40014000/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:658 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:659 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:660 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40014400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:664 */
|
|
timers16: timers@40014400 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:665 */
|
|
reg = < 0x40014400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:666 */
|
|
clocks = < &rcc 0x60 0x20000 >,
|
|
< &rcc 0xa 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:667 */
|
|
resets = < &rctl 0x811 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:669 */
|
|
interrupts = < 0x19 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:670 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:671 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:672 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:673 */
|
|
|
|
/* node '/soc/timers@40014400/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:675 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:676 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:677 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:678 */
|
|
};
|
|
|
|
/* node '/soc/timers@40014400/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:681 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:682 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:683 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/timers@40014800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:687 */
|
|
timers17: timers@40014800 {
|
|
compatible = "st,stm32-timers"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:688 */
|
|
reg = < 0x40014800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:689 */
|
|
clocks = < &rcc 0x60 0x40000 >,
|
|
< &rcc 0xa 0xff >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:690 */
|
|
resets = < &rctl 0x812 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:692 */
|
|
interrupts = < 0x1a 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:693 */
|
|
interrupt-names = "global"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:694 */
|
|
st,prescaler = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:695 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:696 */
|
|
|
|
/* node '/soc/timers@40014800/pwm' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:698 */
|
|
pwm {
|
|
compatible = "st,stm32-pwm"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:699 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:700 */
|
|
#pwm-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:701 */
|
|
};
|
|
|
|
/* node '/soc/timers@40014800/counter' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:704 */
|
|
counter {
|
|
compatible = "st,stm32-counter"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:705 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:706 */
|
|
};
|
|
};
|
|
|
|
/* node '/soc/rtc@40002800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:710 */
|
|
rtc: rtc@40002800 {
|
|
compatible = "st,stm32-rtc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:711 */
|
|
reg = < 0x40002800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:712 */
|
|
interrupts = < 0x29 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:713 */
|
|
prescaler = < 0x8000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:715 */
|
|
alarms-count = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:716 */
|
|
alrm-exti-line = < 0x11 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:717 */
|
|
clocks = < &rcc 0x58 0x400 >,
|
|
< &rcc 0x3 0x2280090 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:162 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:164 */
|
|
};
|
|
|
|
/* node '/soc/rng@50060800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:721 */
|
|
rng: rng@50060800 {
|
|
compatible = "st,stm32-rng"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:722 */
|
|
reg = < 0x50060800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:723 */
|
|
interrupts = < 0x5a 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:724 */
|
|
clocks = < &rcc 0x4c 0x4000000 >,
|
|
< &rcc 0x5 0x3a0088 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:98 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:100 */
|
|
};
|
|
|
|
/* node '/soc/usb@40005c00' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:729 */
|
|
usb: usb@40005c00 {
|
|
compatible = "st,stm32-usb"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:730 */
|
|
reg = < 0x40005c00 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:731 */
|
|
interrupts = < 0x14 0x0 >,
|
|
< 0x13 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:732 */
|
|
interrupt-names = "usb",
|
|
"usbhp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:733 */
|
|
num-bidir-endpoints = < 0x8 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:734 */
|
|
ram-size = < 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:735 */
|
|
maximum-speed = "full-speed"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:736 */
|
|
phys = < &usb_fs_phy >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:737 */
|
|
clocks = < &rcc 0x58 0x800000 >,
|
|
< &rcc 0x5 0x3a0088 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:738 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:740 */
|
|
};
|
|
|
|
/* node '/soc/dma@40020000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:743 */
|
|
dma1: dma@40020000 {
|
|
compatible = "st,stm32-dma-v2"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:744 */
|
|
#dma-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:745 */
|
|
reg = < 0x40020000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:746 */
|
|
clocks = < &rcc 0x48 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:747 */
|
|
dma-offset = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:748 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:749 */
|
|
interrupts = < 0xb 0x0 0xc 0x0 0xd 0x0 0xe 0x0 0xf 0x0 0x10 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:14 */
|
|
dma-requests = < 0x6 >; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:15 */
|
|
phandle = < 0x1a >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:785 */
|
|
};
|
|
|
|
/* node '/soc/dma@40020400' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:752 */
|
|
dma2: dma@40020400 {
|
|
compatible = "st,stm32-dma-v2"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:753 */
|
|
#dma-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:754 */
|
|
reg = < 0x40020400 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:755 */
|
|
clocks = < &rcc 0x48 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:756 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:757 */
|
|
interrupts = < 0x38 0x0 0x39 0x0 0x3a 0x0 0x3b 0x0 0x3c 0x0 0x61 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:19 */
|
|
dma-requests = < 0x6 >; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:20 */
|
|
dma-offset = < 0x6 >; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:21 */
|
|
};
|
|
|
|
/* node '/soc/dmamux@40020800' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:760 */
|
|
dmamux1: dmamux@40020800 {
|
|
compatible = "st,stm32-dmamux"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:761 */
|
|
#dma-cells = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:762 */
|
|
reg = < 0x40020800 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:763 */
|
|
interrupts = < 0x5e 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:764 */
|
|
clocks = < &rcc 0x48 0x4 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:765 */
|
|
dma-generators = < 0x4 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:766 */
|
|
dma-requests = < 0x6f >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:767 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:768 */
|
|
dma-channels = < 0xc >; /* in zephyr/dts/arm/st/g4/stm32g431.dtsi:25 */
|
|
};
|
|
|
|
/* node '/soc/ucpd@4000a000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:771 */
|
|
ucpd1: ucpd@4000a000 {
|
|
compatible = "st,stm32-ucpd"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:772 */
|
|
reg = < 0x4000a000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:773 */
|
|
clocks = < &rcc 0x58 0x10 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:774 */
|
|
interrupts = < 0x3f 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:775 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:776 */
|
|
};
|
|
|
|
/* node '/soc/sai1@40015404' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:779 */
|
|
sai1_a: sai1@40015404 {
|
|
compatible = "st,stm32-sai"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:780 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:781 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:782 */
|
|
reg = < 0x40015404 0x20 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:783 */
|
|
clocks = < &rcc 0x60 0x200000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:784 */
|
|
dmas = < &dma1 0x1 0x6c 0x22800 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:785 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:787 */
|
|
};
|
|
|
|
/* node '/soc/sai1@40015424' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:790 */
|
|
sai1_b: sai1@40015424 {
|
|
compatible = "st,stm32-sai"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:791 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:792 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:793 */
|
|
reg = < 0x40015424 0x20 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:794 */
|
|
clocks = < &rcc 0x60 0x200000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:795 */
|
|
dmas = < &dma1 0x2 0x6d 0x22800 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:796 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:798 */
|
|
};
|
|
|
|
/* node '/soc/opamp1@40010300' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:801 */
|
|
opamp1: opamp1@40010300 {
|
|
compatible = "st,stm32g4-opamp",
|
|
"st,stm32-opamp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:802 */
|
|
reg = < 0x40010300 0x18 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:803 */
|
|
clocks = < &rcc 0x60 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:804 */
|
|
clock-names = "opampx"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:805 */
|
|
programmable-gain = "OPAMP_GAIN_1",
|
|
"OPAMP_GAIN_2",
|
|
"OPAMP_GAIN_3",
|
|
"OPAMP_GAIN_4",
|
|
"OPAMP_GAIN_7",
|
|
"OPAMP_GAIN_8",
|
|
"OPAMP_GAIN_15",
|
|
"OPAMP_GAIN_16",
|
|
"OPAMP_GAIN_31",
|
|
"OPAMP_GAIN_32",
|
|
"OPAMP_GAIN_63",
|
|
"OPAMP_GAIN_64"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:806 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:812 */
|
|
};
|
|
|
|
/* node '/soc/opamp2@40010304' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:815 */
|
|
opamp2: opamp2@40010304 {
|
|
compatible = "st,stm32g4-opamp",
|
|
"st,stm32-opamp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:816 */
|
|
reg = < 0x40010304 0x18 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:817 */
|
|
clocks = < &rcc 0x60 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:818 */
|
|
clock-names = "opampx"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:819 */
|
|
programmable-gain = "OPAMP_GAIN_1",
|
|
"OPAMP_GAIN_2",
|
|
"OPAMP_GAIN_3",
|
|
"OPAMP_GAIN_4",
|
|
"OPAMP_GAIN_7",
|
|
"OPAMP_GAIN_8",
|
|
"OPAMP_GAIN_15",
|
|
"OPAMP_GAIN_16",
|
|
"OPAMP_GAIN_31",
|
|
"OPAMP_GAIN_32",
|
|
"OPAMP_GAIN_63",
|
|
"OPAMP_GAIN_64"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:820 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:826 */
|
|
};
|
|
|
|
/* node '/soc/opamp3@40010308' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:829 */
|
|
opamp3: opamp3@40010308 {
|
|
compatible = "st,stm32g4-opamp",
|
|
"st,stm32-opamp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:830 */
|
|
reg = < 0x40010308 0x18 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:831 */
|
|
clocks = < &rcc 0x60 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:832 */
|
|
clock-names = "opampx"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:833 */
|
|
programmable-gain = "OPAMP_GAIN_1",
|
|
"OPAMP_GAIN_2",
|
|
"OPAMP_GAIN_3",
|
|
"OPAMP_GAIN_4",
|
|
"OPAMP_GAIN_7",
|
|
"OPAMP_GAIN_8",
|
|
"OPAMP_GAIN_15",
|
|
"OPAMP_GAIN_16",
|
|
"OPAMP_GAIN_31",
|
|
"OPAMP_GAIN_32",
|
|
"OPAMP_GAIN_63",
|
|
"OPAMP_GAIN_64"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:834 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:840 */
|
|
};
|
|
|
|
/* node '/soc/comparator@40010200' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:843 */
|
|
comp1: comparator@40010200 {
|
|
compatible = "st,stm32g4-comp",
|
|
"st,stm32-comp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:844 */
|
|
reg = < 0x40010200 0x4 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:845 */
|
|
interrupts = < 0x40 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:846 */
|
|
st,exti-line = < 0x15 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:847 */
|
|
clocks = < &rcc 0x60 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:848 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:849 */
|
|
};
|
|
|
|
/* node '/soc/comparator@40010204' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:852 */
|
|
comp2: comparator@40010204 {
|
|
compatible = "st,stm32g4-comp",
|
|
"st,stm32-comp"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:853 */
|
|
reg = < 0x40010204 0x4 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:854 */
|
|
interrupts = < 0x40 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:855 */
|
|
st,exti-line = < 0x16 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:856 */
|
|
clocks = < &rcc 0x60 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:857 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:858 */
|
|
};
|
|
|
|
/* node '/soc/crc@40023000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:861 */
|
|
crc: crc@40023000 {
|
|
compatible = "st,stm32-crc"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:862 */
|
|
reg = < 0x40023000 0x400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:863 */
|
|
clocks = < &rcc 0x48 0x1000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:864 */
|
|
resets = < &rctl 0x50c >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:865 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:866 */
|
|
};
|
|
};
|
|
|
|
/* node '/cpus' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:31 */
|
|
cpus {
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:32 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:33 */
|
|
|
|
/* node '/cpus/cpu@0' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:35 */
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:36 */
|
|
compatible = "arm,cortex-m4f"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:37 */
|
|
reg = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:38 */
|
|
cpu-power-states = < &stop0 &stop1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:39 */
|
|
};
|
|
|
|
/* node '/cpus/power-states' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:42 */
|
|
power-states {
|
|
|
|
/* node '/cpus/power-states/state0' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:43 */
|
|
stop0: state0 {
|
|
compatible = "zephyr,power-state"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:44 */
|
|
power-state-name = "suspend-to-idle"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:45 */
|
|
substate-id = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:46 */
|
|
min-residency-us = < 0x14 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:47 */
|
|
phandle = < 0x1b >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:39 */
|
|
};
|
|
|
|
/* node '/cpus/power-states/state1' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:50 */
|
|
stop1: state1 {
|
|
compatible = "zephyr,power-state"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:51 */
|
|
power-state-name = "suspend-to-idle"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:52 */
|
|
substate-id = < 0x2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:53 */
|
|
min-residency-us = < 0x64 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:54 */
|
|
phandle = < 0x1c >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:39 */
|
|
};
|
|
};
|
|
};
|
|
|
|
/* node '/memory@20000000' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:59 */
|
|
sram0: memory@20000000 {
|
|
compatible = "zephyr,memory-region",
|
|
"mmio-sram"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:60 */
|
|
zephyr,memory-region = "SRAM0"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:61 */
|
|
reg = < 0x20000000 0x8000 >; /* in zephyr/dts/arm/st/g4/stm32g431Xb.dtsi:10 */
|
|
};
|
|
|
|
/* node '/clocks' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:64 */
|
|
clocks {
|
|
|
|
/* node '/clocks/clk-hse' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:65 */
|
|
clk_hse: clk-hse {
|
|
#clock-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:66 */
|
|
compatible = "st,stm32-hse-clock"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:67 */
|
|
clock-frequency = < 0x16e3600 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:75 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:76 */
|
|
phandle = < 0x1d >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:85 */
|
|
};
|
|
|
|
/* node '/clocks/clk-hsi' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:71 */
|
|
clk_hsi: clk-hsi {
|
|
#clock-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:72 */
|
|
compatible = "fixed-clock"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:73 */
|
|
clock-frequency = < 0xf42400 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:74 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:75 */
|
|
};
|
|
|
|
/* node '/clocks/clk-hsi48' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:78 */
|
|
clk_hsi48: clk-hsi48 {
|
|
#clock-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:79 */
|
|
compatible = "fixed-clock"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:80 */
|
|
clock-frequency = < 0x2dc6c00 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:81 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:71 */
|
|
};
|
|
|
|
/* node '/clocks/clk-lse' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:85 */
|
|
clk_lse: clk-lse {
|
|
#clock-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:86 */
|
|
compatible = "st,stm32-lse-clock"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:87 */
|
|
clock-frequency = < 0x8000 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:88 */
|
|
driving-capability = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:89 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:67 */
|
|
};
|
|
|
|
/* node '/clocks/clk-lsi' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:93 */
|
|
clk_lsi: clk-lsi {
|
|
#clock-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:94 */
|
|
compatible = "fixed-clock"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:95 */
|
|
clock-frequency = < 0x7d00 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:96 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:63 */
|
|
};
|
|
|
|
/* node '/clocks/pll' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:100 */
|
|
pll: pll {
|
|
#clock-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:101 */
|
|
compatible = "st,stm32g4-pll-clock"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:102 */
|
|
div-m = < 0x6 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:80 */
|
|
mul-n = < 0x55 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:81 */
|
|
div-p = < 0x7 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:82 */
|
|
div-q = < 0x2 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:83 */
|
|
div-r = < 0x2 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:84 */
|
|
clocks = < &clk_hse >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:85 */
|
|
status = "okay"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:86 */
|
|
phandle = < 0x4 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:90 */
|
|
};
|
|
};
|
|
|
|
/* node '/dietemp' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:870 */
|
|
die_temp: dietemp {
|
|
compatible = "st,stm32-temp-cal"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:871 */
|
|
nvmem-cells = < &ts_cal1_otp >,
|
|
< &ts_cal2_otp >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:872 */
|
|
nvmem-cell-names = "TS_CAL1",
|
|
"TS_CAL2"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:873 */
|
|
ts-cal1-temp = < 0x1e >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:874 */
|
|
ts-cal2-temp = < 0x82 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:875 */
|
|
ts-cal-vrefanalog = < 0xbb8 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:876 */
|
|
io-channels = < &adc1 0x10 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:877 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:878 */
|
|
};
|
|
|
|
/* node '/vref' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:881 */
|
|
vref: vref {
|
|
compatible = "st,stm32-vref"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:882 */
|
|
nvmem-cells = < &vrefint_otp >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:883 */
|
|
vrefint-cal-mv = < 0xbb8 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:884 */
|
|
io-channels = < &adc1 0x12 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:885 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:886 */
|
|
};
|
|
|
|
/* node '/vbat' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:889 */
|
|
vbat: vbat {
|
|
compatible = "st,stm32-vbat"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:890 */
|
|
ratio = < 0x3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:891 */
|
|
io-channels = < &adc1 0x11 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:892 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:893 */
|
|
};
|
|
|
|
/* node '/usbphy' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:896 */
|
|
usb_fs_phy: usbphy {
|
|
compatible = "usb-nop-xceiv"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:897 */
|
|
#phy-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:898 */
|
|
phandle = < 0x19 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:737 */
|
|
};
|
|
|
|
/* node '/smbus1' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:901 */
|
|
smbus1: smbus1 {
|
|
compatible = "st,stm32-smbus"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:902 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:903 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:904 */
|
|
i2c = < &i2c1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:905 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:906 */
|
|
};
|
|
|
|
/* node '/smbus2' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:909 */
|
|
smbus2: smbus2 {
|
|
compatible = "st,stm32-smbus"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:910 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:911 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:912 */
|
|
i2c = < &i2c2 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:913 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:914 */
|
|
};
|
|
|
|
/* node '/smbus3' defined in zephyr/dts/arm/st/g4/stm32g4.dtsi:917 */
|
|
smbus3: smbus3 {
|
|
compatible = "st,stm32-smbus"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:918 */
|
|
#address-cells = < 0x1 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:919 */
|
|
#size-cells = < 0x0 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:920 */
|
|
i2c = < &i2c3 >; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:921 */
|
|
status = "disabled"; /* in zephyr/dts/arm/st/g4/stm32g4.dtsi:922 */
|
|
};
|
|
|
|
/* node '/connector' defined in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:10 */
|
|
arduino_header: connector {
|
|
compatible = "arduino-header-r3"; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:11 */
|
|
#gpio-cells = < 0x2 >; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:12 */
|
|
gpio-map-mask = < 0xffffffff 0xffffffc0 >; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:13 */
|
|
gpio-map-pass-thru = < 0x0 0x3f >; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:14 */
|
|
gpio-map = < 0x0 0x0 &gpioa 0x0 0x0 >,
|
|
< 0x1 0x0 &gpioa 0x1 0x0 >,
|
|
< 0x2 0x0 &gpioa 0x4 0x0 >,
|
|
< 0x3 0x0 &gpiob 0x0 0x0 >,
|
|
< 0x4 0x0 &gpioc 0x1 0x0 >,
|
|
< 0x5 0x0 &gpioc 0x0 0x0 >,
|
|
< 0x6 0x0 &gpioc 0x5 0x0 >,
|
|
< 0x7 0x0 &gpioc 0x4 0x0 >,
|
|
< 0x8 0x0 &gpioa 0xa 0x0 >,
|
|
< 0x9 0x0 &gpiob 0x3 0x0 >,
|
|
< 0xa 0x0 &gpiob 0x5 0x0 >,
|
|
< 0xb 0x0 &gpiob 0x4 0x0 >,
|
|
< 0xc 0x0 &gpiob 0xa 0x0 >,
|
|
< 0xd 0x0 &gpioa 0x8 0x0 >,
|
|
< 0xe 0x0 &gpioa 0x9 0x0 >,
|
|
< 0xf 0x0 &gpioc 0x7 0x0 >,
|
|
< 0x10 0x0 &gpiob 0x6 0x0 >,
|
|
< 0x11 0x0 &gpioa 0x7 0x0 >,
|
|
< 0x12 0x0 &gpioa 0x6 0x0 >,
|
|
< 0x13 0x0 &gpioa 0x5 0x0 >,
|
|
< 0x14 0x0 &gpiob 0x9 0x0 >,
|
|
< 0x15 0x0 &gpiob 0x8 0x0 >; /* in zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi:15 */
|
|
};
|
|
|
|
/* node '/st-morpho-header' defined in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:10 */
|
|
st_morpho_header: st-morpho-header {
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compatible = "st-morpho-header"; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:11 */
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#gpio-cells = < 0x2 >; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:12 */
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gpio-map-mask = < 0xff 0x0 >; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:13 */
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gpio-map-pass-thru = < 0x0 0x7f >; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:14 */
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gpio-map = < 0x0 0x0 &gpioc 0xa 0x0 >,
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< 0x1 0x0 &gpioc 0xb 0x0 >,
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< 0x2 0x0 &gpioc 0xc 0x0 >,
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< 0x3 0x0 &gpiod 0x2 0x0 >,
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< 0xc 0x0 &gpioa 0xd 0x0 >,
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< 0xe 0x0 &gpioa 0xe 0x0 >,
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< 0x10 0x0 &gpioa 0xf 0x0 >,
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< 0x14 0x0 &gpiob 0x7 0x0 >,
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< 0x16 0x0 &gpioc 0xd 0x0 >,
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< 0x18 0x0 &gpioc 0xe 0x0 >,
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< 0x1a 0x0 &gpioc 0xf 0x0 >,
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< 0x1b 0x0 &gpioa 0x0 0x0 >,
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< 0x1c 0x0 &gpiof 0x0 0x0 >,
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< 0x1d 0x0 &gpioa 0x1 0x0 >,
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< 0x1e 0x0 &gpiof 0x1 0x0 >,
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< 0x1f 0x0 &gpioa 0x4 0x0 >,
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< 0x21 0x0 &gpiob 0x0 0x0 >,
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< 0x22 0x0 &gpioc 0x2 0x0 >,
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< 0x23 0x0 &gpioc 0x1 0x0 >,
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< 0x24 0x0 &gpioc 0x3 0x0 >,
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< 0x25 0x0 &gpioc 0x0 0x0 >,
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< 0x48 0x0 &gpioc 0x9 0x0 >,
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< 0x49 0x0 &gpioc 0x8 0x0 >,
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< 0x4a 0x0 &gpiob 0x8 0x0 >,
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< 0x4b 0x0 &gpioc 0x6 0x0 >,
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< 0x4c 0x0 &gpiob 0x9 0x0 >,
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< 0x4d 0x0 &gpioc 0x5 0x0 >,
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< 0x52 0x0 &gpiob 0xd 0x0 >,
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< 0x53 0x0 &gpioa 0xc 0x0 >,
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< 0x54 0x0 &gpiob 0xe 0x0 >,
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< 0x55 0x0 &gpioa 0xb 0x0 >,
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< 0x56 0x0 &gpiob 0xf 0x0 >,
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< 0x57 0x0 &gpiob 0xc 0x0 >,
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< 0x58 0x0 &gpiob 0x6 0x0 >,
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< 0x59 0x0 &gpiob 0xb 0x0 >,
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< 0x5a 0x0 &gpioc 0x7 0x0 >,
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< 0x5c 0x0 &gpioa 0x9 0x0 >,
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< 0x5d 0x0 &gpiob 0x2 0x0 >,
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< 0x5e 0x0 &gpioa 0x8 0x0 >,
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< 0x5f 0x0 &gpiob 0x1 0x0 >,
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< 0x60 0x0 &gpiob 0xa 0x0 >,
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< 0x61 0x0 &gpioa 0x7 0x0 >,
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< 0x62 0x0 &gpiob 0x4 0x0 >,
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< 0x63 0x0 &gpioa 0x6 0x0 >,
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< 0x64 0x0 &gpiob 0x5 0x0 >,
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< 0x65 0x0 &gpioa 0x5 0x0 >,
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< 0x66 0x0 &gpiob 0x3 0x0 >,
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< 0x68 0x0 &gpioa 0xa 0x0 >,
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< 0x69 0x0 &gpioc 0x4 0x0 >,
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< 0x6a 0x0 &gpioa 0x2 0x0 >,
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< 0x6c 0x0 &gpioa 0x3 0x0 >; /* in zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi:15 */
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};
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/* node '/leds' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:26 */
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leds: leds {
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compatible = "gpio-leds"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:27 */
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|
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/* node '/leds/led_0' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:29 */
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green_led: led_0 {
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gpios = < &gpioa 0x5 0x0 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:30 */
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label = "User LD2"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:31 */
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};
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};
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/* node '/pwmleds' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:35 */
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|
pwmleds {
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compatible = "pwm-leds"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:36 */
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|
|
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/* node '/pwmleds/green_pwm_led' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:38 */
|
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green_pwm_led: green_pwm_led {
|
|
pwms = < &pwm2 0x1 0x1312d00 0x0 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:39 */
|
|
};
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};
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/* node '/gpio_keys' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:43 */
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gpio_keys {
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compatible = "gpio-keys"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:44 */
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|
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/* node '/gpio_keys/button' defined in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:46 */
|
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user_button: button {
|
|
label = "User"; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:47 */
|
|
gpios = < &gpioc 0xd 0x0 >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:48 */
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|
zephyr,code = < 0xb >; /* in zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts:49 */
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|
};
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|
};
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|
};
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