# 0 "/home/jeremy/utat-dev/zephyrproject/zephyr/misc/empty_file.c"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts" 1

/dts-v1/;
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g431Xb.dtsi" 1 3 4

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g431.dtsi" 1 3 4

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 1 3 4
# 11 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/armv7-m.dtsi" 1 3 4

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/common/skeleton.dtsi" 1 3 4
# 9 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/common/skeleton.dtsi" 3 4
/ {
 #address-cells = <1>;
 #size-cells = <1>;

 chosen {};

 aliases {};
};
# 4 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/armv7-m.dtsi" 2 3 4

/ {
 soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  interrupt-parent = <&nvic>;
  ranges;

  nvic: interrupt-controller@e000e100 {
   #address-cells = <1>;
   compatible = "arm,v7m-nvic";
   reg = <0xe000e100 0xc00>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  systick: timer@e000e010 {
   compatible = "arm,armv7m-systick";
   reg = <0xe000e010 0x10>;
  };
 };
};
# 12 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h" 1 3 4
# 9 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32_common_clocks.h" 1 3 4
# 10 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h" 2 3 4
# 13 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/i2c/i2c.h" 1 3 4
# 14 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/gpio/gpio.h" 1 3 4
# 15 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/pwm/pwm.h" 1 3 4
# 16 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 1 3 4
# 9 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 1 3 4
# 19 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 1 3 4
# 34 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 1 3 4
# 18 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 1 3 4
# 1465 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_listify.h" 1 3 4
# 1466 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 2 3 4
# 19 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 203 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal_is_eq.h" 1 3 4
# 204 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 234 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_inc.h" 1 3 4
# 235 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_dec.h" 1 3 4
# 238 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_x2.h" 1 3 4
# 241 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 35 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 2 3 4
# 20 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 2 3 4
# 10 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 2 3 4
# 17 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/pwm/stm32_pwm.h" 1 3 4
# 18 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/dma/stm32_dma.h" 1 3 4
# 19 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h" 1 3 4
# 10 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32-common.h" 1 3 4
# 11 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h" 2 3 4
# 20 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/sensor/qdec_stm32.h" 1 3 4
# 21 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/common/freq.h" 1 3 4
# 22 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/common/mem.h" 1 3 4
# 23 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g4.dtsi" 2 3 4

/ {
 chosen {
  zephyr,crc = &crc;
  zephyr,entropy = &rng;
  zephyr,flash-controller = &flash;
 };

 cpus {
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-m4f";
   reg = <0>;
   cpu-power-states = <&stop0 &stop1>;
  };

  power-states {
   stop0: state0 {
    compatible = "zephyr,power-state";
    power-state-name = "suspend-to-idle";
    substate-id = <1>;
    min-residency-us = <20>;
   };

   stop1: state1 {
    substate-id = <2>;
    min-residency-us = <100>;
   };
  };
 };

 sram0: memory@20000000 {
  compatible = "zephyr,memory-region", "mmio-sram";
  zephyr,memory-region = "SRAM0";
 };

 clocks {
  clk_hse: clk-hse {
   #clock-cells = <0>;
   compatible = "st,stm32-hse-clock";
   status = "disabled";
  };

  clk_hsi: clk-hsi {
   compatible = "fixed-clock";
   clock-frequency = <(((16) * 1000) * 1000)>;
  };

  clk_hsi48: clk-hsi48 {
   clock-frequency = <(((48) * 1000) * 1000)>;
  };

  clk_lse: clk-lse {
   compatible = "st,stm32-lse-clock";
   clock-frequency = <32768>;
   driving-capability = <0>;
  };

  clk_lsi: clk-lsi {
   clock-frequency = <((32) * 1000)>;
  };

  pll: pll {
   compatible = "st,stm32g4-pll-clock";
  };
 };

 soc {

  adc1: adc@50000000 {
   compatible = "st,stm32-adc";
   reg = <0x50000000 0x100>;
   clocks = <&rcc (0x04c) (1 << 13)>;
   clock-names = "adcx";
   interrupts = <18 0>;
   #io-channel-cells = <1>;
   st,adc-resolutions = <12 10 8 6>;
   sampling-times = <3 7 13 25 48 93 248 641>;
   st,adc-sequencer = "programmable";
   st,adc-oversampler = "minimal";
   st,adc-internal-regulator = "startup-sw-delay";
   st,adc-has-deep-powerdown;
   st,adc-has-differential-support;
   st,adc-has-injected-support;
  };

  adc2: adc@50000100 {
   reg = <0x50000100 0x100>;
  };

  dac1: dac@50000800 {
   compatible = "st,stm32-dac";
   reg = <0x50000800 0x400>;
   clocks = <&rcc (0x04c) (1 << 16)>;
  };

  dac3: dac@50001000 {
   reg = <0x50001000 0x400>;
   clocks = <&rcc (0x04c) (1 << 18)>;
  };

  flash: flash-controller@40022000 {
   compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller";
   reg = <0x40022000 0x400>;
   interrupts = <3 0>;
   clocks = <&rcc (0x048) (1 << 8)>;

   #size-cells = <1>;
   ranges;

   flash0: flash@8000000 {
    compatible = "st,stm32-nv-flash", "soc-nv-flash";
    #address-cells = <1>;
    #size-cells = <1>;
    write-block-size = <8>;
    erase-block-size = <2048>;

    max-erase-time = <25>;
   };

   st_nvm_user_otp: flash@1fff7000 {
    compatible = "st,stm32-nvm-otp";
    reg = <0x1fff7000 ((1) * 1024)>;
    status = "disabled";
   };

   flash@1fff7500 {
    reg = <0x1fff7500 768>;

    nvmem-layout {
     compatible = "fixed-layout";
     #address-cells = <1>;
     #size-cells = <1>;

     ts_cal1_otp: ts-cal1@a8 {
      reg = <0xa8 0x2>;
      #nvmem-cell-cells = <0>;
      read-only;
     };

     vrefint_otp: vrefint@aa {
      reg = <0xaa 0x2>;
     };

     ts_cal2_otp: ts-cal2@ca {
      reg = <0xca 0x2>;
     };
    };
   };
  };

  rcc: rcc@40021000 {
   compatible = "st,stm32-rcc";
   #clock-cells = <2>;
   reg = <0x40021000 0x400>;
   undershoot-prevention;

   rctl: reset-controller {
    compatible = "st,stm32-rcc-rctl";
    #reset-cells = <1>;
   };
  };

  exti: interrupt-controller@40010400 {
   compatible = "st,stm32-exti";
   #interrupt-cells = <1>;
   #address-cells = <0>;
   reg = <0x40010400 0x400>;
   clocks = <&rcc (0x060) (1 << 0)>;
   num-lines = <64>;
   interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
         <10 0>, <23 0>, <40 0>;
   interrupt-names = "line0", "line1", "line2-TSC", "line3",
       "line4", "line5-9", "line10-15";
   line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
          <4 1>, <5 5>, <10 6>;
  };

  pinctrl: pin-controller@48000000 {
   compatible = "st,stm32-pinctrl";
   reg = <0x48000000 0x2000>;

   gpioa: gpio@48000000 {
    compatible = "st,stm32-gpio";
    gpio-controller;
    #gpio-cells = <2>;
    reg = <0x48000000 0x400>;
    clocks = <&rcc (0x04c) (1 << 0)>;
   };

   gpiob: gpio@48000400 {
    reg = <0x48000400 0x400>;
    clocks = <&rcc (0x04c) (1 << 1)>;
   };

   gpioc: gpio@48000800 {
    reg = <0x48000800 0x400>;
    clocks = <&rcc (0x04c) (1 << 2)>;
   };

   gpiod: gpio@48000c00 {
    reg = <0x48000c00 0x400>;
    clocks = <&rcc (0x04c) (1 << 3)>;
   };

   gpioe: gpio@48001000 {
    reg = <0x48001000 0x400>;
    clocks = <&rcc (0x04c) (1 << 4)>;
   };

   gpiof: gpio@48001400 {
    reg = <0x48001400 0x400>;
    clocks = <&rcc (0x04c) (1 << 5)>;
   };

   gpiog: gpio@48001800 {
    reg = <0x48001800 0x400>;
    clocks = <&rcc (0x04c) (1 << 6)>;
   };
  };

  usart1: serial@40013800 {
   compatible = "st,stm32-usart", "st,stm32-uart";
   reg = <0x40013800 0x400>;
   clocks = <&rcc (0x060) (1 << 14)>;
   resets = <&rctl (((0x40) << 5U) | (14))>;
   interrupts = <37 0>;
  };

  usart2: serial@40004400 {
   reg = <0x40004400 0x400>;
   clocks = <&rcc (0x058) (1 << 17)>;
   resets = <&rctl (((0x38) << 5U) | (17))>;
   interrupts = <38 0>;
  };

  usart3: serial@40004800 {
   reg = <0x40004800 0x400>;
   clocks = <&rcc (0x058) (1 << 18)>;
   resets = <&rctl (((0x38) << 5U) | (18))>;
   interrupts = <39 0>;
  };

  uart4: serial@40004c00 {
   compatible = "st,stm32-uart";
   reg = <0x40004c00 0x400>;
   clocks = <&rcc (0x058) (1 << 19)>;
   resets = <&rctl (((0x38) << 5U) | (19))>;
   interrupts = <52 0>;
  };

  lpuart1: serial@40008000 {
   compatible = "st,stm32-lpuart", "st,stm32-uart";
   reg = <0x40008000 0x400>;
   clocks = <&rcc (0x05c) (1 << 0)>;
   resets = <&rctl (((0x3C) << 5U) | (0))>;
   interrupts = <91 0>;
  };

  iwdg: watchdog@40003000 {
   compatible = "st,stm32-watchdog";
   reg = <0x40003000 0x400>;
  };

  wwdg: watchdog@40002c00 {
   compatible = "st,stm32-window-watchdog";
   reg = <0x40002c00 0x400>;
   clocks = <&rcc (0x058) (1 << 11)>;
   interrupts = <0 0>;
  };

  i2c1: i2c@40005400 {
   compatible = "st,stm32-i2c-v2";
   clock-frequency = <100000>;
   #size-cells = <0>;
   reg = <0x40005400 0x400>;
   clocks = <&rcc (0x058) (1 << 21)>;
   interrupts = <31 0>, <32 0>;
   interrupt-names = "event", "error";
  };

  i2c2: i2c@40005800 {
   reg = <0x40005800 0x400>;
   clocks = <&rcc (0x058) (1 << 22)>;
   interrupts = <33 0>, <34 0>;
  };

  i2c3: i2c@40007800 {
   reg = <0x40007800 0x400>;
   clocks = <&rcc (0x058) (1 << 30)>;
   interrupts = <92 0>, <93 0>;
  };

  spi1: spi@40013000 {
   compatible = "st,stm32-spi-fifo", "st,stm32-spi";
   reg = <0x40013000 0x400>;
   interrupts = <35 0>;
   clocks = <&rcc (0x060) (1 << 12)>;
   st,spi-data-width = "full-4-to-16-bit";
  };

  spi2: spi@40003800 {
   reg = <0x40003800 0x400>;
   clocks = <&rcc (0x058) (1 << 14)>;
   interrupts = <36 0>;
  };

  spi3: spi@40003c00 {
   reg = <0x40003c00 0x400>;
   clocks = <&rcc (0x058) (1 << 15)>;
   interrupts = <51 0>;
  };

  fdcan1: can@40006400 {
   compatible = "st,stm32-fdcan";
   reg = <0x40006400 0x400>, <0x4000a400 0x350>;
   reg-names = "m_can", "message_ram";
   interrupts = <21 0>, <22 0>;
   interrupt-names = "int0", "int1";
   clocks = <&rcc (0x058) (1 << 25)>;
   bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
  };

  lptim1: timers@40007c00 {
   compatible = "st,stm32-lptim";
   clocks = <&rcc (0x058) (1 << 31)>;
   resets = <&rctl (((0x38) << 5U) | (31))>;
   reg = <0x40007c00 0x400>;
   interrupts = <49 0>;
   interrupt-names = "wakeup";
  };

  timers1: timers@40012c00 {
   compatible = "st,stm32-timers";
   reg = <0x40012c00 0x400>;
   clocks = <&rcc (0x060) (1 << 11)>,
     <&rcc (((((((0x003 + 1) + 1) + 1) + 1) + 1) + 1) + 1) 0xFF>;
   resets = <&rctl (((0x40) << 5U) | (11))>;
   interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
   interrupt-names = "brk", "up", "trgcom", "cc";
   st,prescaler = <0>;

   pwm {
    compatible = "st,stm32-pwm";
    #pwm-cells = <3>;
   };

   counter {
    compatible = "st,stm32-counter";
   };

   qdec {
    compatible = "st,stm32-qdec";
    st,input-filter-level = <0>;
   };
  };

  timers2: timers@40000000 {
   reg = <0x40000000 0x400>;
   clocks = <&rcc (0x058) (1 << 0)>,
     <&rcc ((((((0x003 + 1) + 1) + 1) + 1) + 1) + 1) 0xFF>;
   resets = <&rctl (((0x38) << 5U) | (0))>;
   interrupts = <28 0>;
   interrupt-names = "global";

   counter {
   };

   pwm {
   };

   qdec {
   };
  };

  timers3: timers@40000400 {
   reg = <0x40000400 0x400>;
   clocks = <&rcc (0x058) (1 << 1)>,
   resets = <&rctl (((0x38) << 5U) | (1))>;
   interrupts = <29 0>;

   counter {
   };

   pwm {
   };

   qdec {
   };
  };

  timers4: timers@40000800 {
   reg = <0x40000800 0x400>;
   clocks = <&rcc (0x058) (1 << 2)>,
   resets = <&rctl (((0x38) << 5U) | (2))>;
   interrupts = <30 0>;

   counter {
   };

   pwm {
   };

   qdec {
   };
  };

  timers6: timers@40001000 {
   reg = <0x40001000 0x400>;
   clocks = <&rcc (0x058) (1 << 4)>,
   resets = <&rctl (((0x38) << 5U) | (4))>;
   interrupts = <54 0>;

   counter {
   };
  };

  timers7: timers@40001400 {
   reg = <0x40001400 0x400>;
   clocks = <&rcc (0x058) (1 << 5)>,
   resets = <&rctl (((0x38) << 5U) | (5))>;
   interrupts = <55 0>;

   counter {
   };
  };

  timers8: timers@40013400 {
   reg = <0x40013400 0x400>;
   clocks = <&rcc (0x060) (1 << 13)>,
   resets = <&rctl (((0x40) << 5U) | (13))>;
   interrupts = <43 0>, <44 0>, <45 0>, <46 0>;

   pwm {
   };

   counter {
   };

   qdec {
   };
  };

  timers15: timers@40014000 {
   reg = <0x40014000 0x400>;
   clocks = <&rcc (0x060) (1 << 16)>,
   resets = <&rctl (((0x40) << 5U) | (16))>;
   interrupts = <24 0>;

   pwm {
   };

   counter {
   };
  };

  timers16: timers@40014400 {
   reg = <0x40014400 0x400>;
   clocks = <&rcc (0x060) (1 << 17)>,
   resets = <&rctl (((0x40) << 5U) | (17))>;
   interrupts = <25 0>;

   pwm {
   };

   counter {
   };
  };

  timers17: timers@40014800 {
   reg = <0x40014800 0x400>;
   clocks = <&rcc (0x060) (1 << 18)>,
   resets = <&rctl (((0x40) << 5U) | (18))>;
   interrupts = <26 0>;

   pwm {
   };

   counter {
   };
  };

  rtc: rtc@40002800 {
   compatible = "st,stm32-rtc";
   reg = <0x40002800 0x400>;
   interrupts = <41 0>;
   clocks = <&rcc (0x058) (1 << 10)>;
   prescaler = <32768>;
   alarms-count = <2>;
   alrm-exti-line = <17>;
  };

  rng: rng@50060800 {
   compatible = "st,stm32-rng";
   reg = <0x50060800 0x400>;
   interrupts = <90 0>;
   clocks = <&rcc (0x04c) (1 << 26)>;
  };

  usb: usb@40005c00 {
   compatible = "st,stm32-usb";
   reg = <0x40005c00 0x400>;
   interrupts = <20 0>, <19 0>;
   interrupt-names = "usb", "usbhp";
   num-bidir-endpoints = <8>;
   ram-size = <1024>;
   maximum-speed = "full-speed";
   phys = <&usb_fs_phy>;
   clocks = <&rcc (0x058) (1 << 23)>,
     <&rcc ((0x003 + 1) + 1) ((((0x88) & 0xFFFFU) << 0U) | (((26) & 0x1FU) << 16U) | ((((27) - (26)) & 0x3U) << 21U) | ((((0)) & 0xFFU) << 24U))>;
  };

  dma1: dma@40020000 {
   compatible = "st,stm32-dma-v2";
   #dma-cells = <3>;
   reg = <0x40020000 0x400>;
   clocks = <&rcc (0x048) (1 << 0)>;
   dma-offset = <0>;
  };

  dma2: dma@40020400 {
   reg = <0x40020400 0x400>;
   clocks = <&rcc (0x048) (1 << 1)>;
  };

  dmamux1: dmamux@40020800 {
   compatible = "st,stm32-dmamux";
   reg = <0x40020800 0x400>;
   interrupts = <94 0>;
   clocks = <&rcc (0x048) (1 << 2)>;
   dma-generators = <4>;
   dma-requests = <111>;
  };

  ucpd1: ucpd@4000a000 {
   compatible = "st,stm32-ucpd";
   reg = <0x4000a000 0x400>;
   clocks = <&rcc (0x058) (1 << 4)>;
   interrupts = <63 0>;
  };

  sai1_a: sai1@40015404 {
   compatible = "st,stm32-sai";
   reg = <0x40015404 0x20>;
   clocks = <&rcc (0x060) (1 << 21)>;
   dmas = <&dma1 1 108 (((0 & 0x1) << 5) | ((2 & 0x3) << 16) |
          (((1 & 0x3) << 11) | ((1 & 0x3) << 13)))>;
  };

  sai1_b: sai1@40015424 {
   reg = <0x40015424 0x20>;
   dmas = <&dma1 2 109 (((0 & 0x1) << 5) | ((2 & 0x3) << 16) |
  };

  opamp1: opamp1@40010300 {
   compatible = "st,stm32g4-opamp", "st,stm32-opamp";
   reg = <0x40010300 0x18>;
   clock-names = "opampx";
   programmable-gain = "OPAMP_GAIN_1", "OPAMP_GAIN_2",
         "OPAMP_GAIN_3", "OPAMP_GAIN_4",
         "OPAMP_GAIN_7", "OPAMP_GAIN_8",
         "OPAMP_GAIN_15", "OPAMP_GAIN_16",
         "OPAMP_GAIN_31", "OPAMP_GAIN_32",
         "OPAMP_GAIN_63", "OPAMP_GAIN_64";
  };

  opamp2: opamp2@40010304 {
   reg = <0x40010304 0x18>;
  };

  opamp3: opamp3@40010308 {
   reg = <0x40010308 0x18>;
  };

  comp1: comparator@40010200 {
   compatible = "st,stm32g4-comp", "st,stm32-comp";
   reg = <0x40010200 0x4>;
   interrupts = <64 0>;
   st,exti-line = <21>;
  };

  comp2: comparator@40010204 {
   reg = <0x40010204 0x4>;
   st,exti-line = <22>;
  };

  crc: crc@40023000 {
   compatible = "st,stm32-crc";
   reg = <0x40023000 0x400>;
   clocks = <&rcc (0x048) (1 << 12)>;
   resets = <&rctl (((0x28) << 5U) | (12))>;
  };
 };

 die_temp: dietemp {
  compatible = "st,stm32-temp-cal";
  nvmem-cells = <&ts_cal1_otp>, <&ts_cal2_otp>;
  nvmem-cell-names = "TS_CAL1", "TS_CAL2";
  ts-cal1-temp = <30>;
  ts-cal2-temp = <130>;
  ts-cal-vrefanalog = <3000>;
  io-channels = <&adc1 16>;
  status = "disabled";
 };

 vref: vref {
  compatible = "st,stm32-vref";
  nvmem-cells = <&vrefint_otp>;
  vrefint-cal-mv = <3000>;
  io-channels = <&adc1 18>;
 };

 vbat: vbat {
  compatible = "st,stm32-vbat";
  ratio = <3>;
  io-channels = <&adc1 17>;
 };

 usb_fs_phy: usbphy {
  compatible = "usb-nop-xceiv";
  #phy-cells = <0>;
 };

 smbus1: smbus1 {
  compatible = "st,stm32-smbus";
  i2c = <&i2c1>;
 };

 smbus2: smbus2 {
  i2c = <&i2c2>;
 };

 smbus3: smbus3 {
  i2c = <&i2c3>;
 };
};

&nvic {
 arm,num-irq-priority-bits = <4>;
};
# 8 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g431.dtsi" 2 3 4

/ {
 soc {
  compatible = "st,stm32g431", "st,stm32g4", "simple-bus";

   interrupts = <11 0 12 0 13 0 14 0 15 0 16 0>;
   dma-requests = <6>;
  };

   interrupts = <56 0 57 0 58 0 59 0 60 0 97 0>;
   dma-offset = <6>;
  };

   dma-channels = <12>;
  };
 };
};
# 8 "/home/jeremy/utat-dev/zephyrproject/zephyr/dts/arm/st/g4/stm32g431Xb.dtsi" 2 3 4

&sram0 {
 reg = <0x20000000 ((32) * 1024)>;
};

&flash0 {
 reg = <0x08000000 ((128) * 1024)>;
 ranges = <0 0x8000000 ((128) * 1024)>;
};
# 9 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts" 2
# 1 "/home/jeremy/utat-dev/zephyrproject/modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi" 1 3 4

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h" 1 3 4
# 10 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h" 3 4
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h" 1 3 4
# 11 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h" 2 3 4
# 8 "/home/jeremy/utat-dev/zephyrproject/modules/hal/stm32/dts/st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi" 2 3 4

&pinctrl {

 /omit-if-no-ref/ adc1_in1_pa0: adc1_in1_pa0 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in2_pa1: adc1_in2_pa1 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in3_pa2: adc1_in3_pa2 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in4_pa3: adc1_in4_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in15_pb0: adc1_in15_pb0 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in12_pb1: adc1_in12_pb1 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in14_pb11: adc1_in14_pb11 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in11_pb12: adc1_in11_pb12 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in5_pb14: adc1_in5_pb14 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in6_pc0: adc1_in6_pc0 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in7_pc1: adc1_in7_pc1 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in8_pc2: adc1_in8_pc2 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in9_pc3: adc1_in9_pc3 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc1_in10_pf0: adc1_in10_pf0 {
  pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in1_pa0: adc2_in1_pa0 {
 };

 /omit-if-no-ref/ adc2_in2_pa1: adc2_in2_pa1 {
 };

 /omit-if-no-ref/ adc2_in17_pa4: adc2_in17_pa4 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in13_pa5: adc2_in13_pa5 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in3_pa6: adc2_in3_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in4_pa7: adc2_in4_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in12_pb2: adc2_in12_pb2 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in14_pb11: adc2_in14_pb11 {
 };

 /omit-if-no-ref/ adc2_in15_pb15: adc2_in15_pb15 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in6_pc0: adc2_in6_pc0 {
 };

 /omit-if-no-ref/ adc2_in7_pc1: adc2_in7_pc1 {
 };

 /omit-if-no-ref/ adc2_in8_pc2: adc2_in8_pc2 {
 };

 /omit-if-no-ref/ adc2_in9_pc3: adc2_in9_pc3 {
 };

 /omit-if-no-ref/ adc2_in5_pc4: adc2_in5_pc4 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in11_pc5: adc2_in11_pc5 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ adc2_in10_pf1: adc2_in10_pf1 {
  pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa0: analog_pa0 {
 };

 /omit-if-no-ref/ analog_pa1: analog_pa1 {
 };

 /omit-if-no-ref/ analog_pa2: analog_pa2 {
 };

 /omit-if-no-ref/ analog_pa3: analog_pa3 {
 };

 /omit-if-no-ref/ analog_pa4: analog_pa4 {
 };

 /omit-if-no-ref/ analog_pa5: analog_pa5 {
 };

 /omit-if-no-ref/ analog_pa6: analog_pa6 {
 };

 /omit-if-no-ref/ analog_pa7: analog_pa7 {
 };

 /omit-if-no-ref/ analog_pa8: analog_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa9: analog_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa10: analog_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa11: analog_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa12: analog_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa13: analog_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa14: analog_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pa15: analog_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb0: analog_pb0 {
 };

 /omit-if-no-ref/ analog_pb1: analog_pb1 {
 };

 /omit-if-no-ref/ analog_pb2: analog_pb2 {
 };

 /omit-if-no-ref/ analog_pb3: analog_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb4: analog_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb5: analog_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb6: analog_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb7: analog_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb8: analog_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb9: analog_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb10: analog_pb10 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb11: analog_pb11 {
 };

 /omit-if-no-ref/ analog_pb12: analog_pb12 {
 };

 /omit-if-no-ref/ analog_pb13: analog_pb13 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pb14: analog_pb14 {
 };

 /omit-if-no-ref/ analog_pb15: analog_pb15 {
 };

 /omit-if-no-ref/ analog_pc0: analog_pc0 {
 };

 /omit-if-no-ref/ analog_pc1: analog_pc1 {
 };

 /omit-if-no-ref/ analog_pc2: analog_pc2 {
 };

 /omit-if-no-ref/ analog_pc3: analog_pc3 {
 };

 /omit-if-no-ref/ analog_pc4: analog_pc4 {
 };

 /omit-if-no-ref/ analog_pc5: analog_pc5 {
 };

 /omit-if-no-ref/ analog_pc6: analog_pc6 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc7: analog_pc7 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc8: analog_pc8 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc9: analog_pc9 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc10: analog_pc10 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc11: analog_pc11 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc12: analog_pc12 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc13: analog_pc13 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc14: analog_pc14 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pc15: analog_pc15 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pd2: analog_pd2 {
  pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ analog_pf0: analog_pf0 {
 };

 /omit-if-no-ref/ analog_pf1: analog_pf1 {
 };

 /omit-if-no-ref/ analog_pg10: analog_pg10 {
  pinmux = <((((('G') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x10) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp1_inm_pa0: comp1_inm_pa0 {
 };

 /omit-if-no-ref/ comp1_inp_pa1: comp1_inp_pa1 {
 };

 /omit-if-no-ref/ comp1_inm_pa4: comp1_inm_pa4 {
 };

 /omit-if-no-ref/ comp1_inp_pb1: comp1_inp_pb1 {
 };

 /omit-if-no-ref/ comp2_inm_pa2: comp2_inm_pa2 {
 };

 /omit-if-no-ref/ comp2_inp_pa3: comp2_inp_pa3 {
 };

 /omit-if-no-ref/ comp2_inm_pa5: comp2_inm_pa5 {
 };

 /omit-if-no-ref/ comp2_inp_pa7: comp2_inp_pa7 {
 };

 /omit-if-no-ref/ comp3_inp_pa0: comp3_inp_pa0 {
 };

 /omit-if-no-ref/ comp3_inm_pc0: comp3_inm_pc0 {
 };

 /omit-if-no-ref/ comp3_inp_pc1: comp3_inp_pc1 {
 };

 /omit-if-no-ref/ comp3_inm_pf1: comp3_inm_pf1 {
 };

 /omit-if-no-ref/ comp4_inp_pb0: comp4_inp_pb0 {
 };

 /omit-if-no-ref/ comp4_inm_pb2: comp4_inm_pb2 {
 };

 /omit-if-no-ref/ comp1_out_pa0: comp1_out_pa0 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp1_out_pa6: comp1_out_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp1_out_pa11: comp1_out_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp1_out_pb8: comp1_out_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp2_out_pa2: comp2_out_pa2 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp2_out_pa7: comp2_out_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp2_out_pa12: comp2_out_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp2_out_pb9: comp2_out_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp3_out_pb7: comp3_out_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp3_out_pb15: comp3_out_pb15 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp3_out_pc2: comp3_out_pc2 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp4_out_pb1: comp4_out_pb1 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp4_out_pb6: comp4_out_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ comp4_out_pb14: comp4_out_pb14 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ dac1_out1_pa4: dac1_out1_pa4 {
 };

 /omit-if-no-ref/ dac1_out2_pa5: dac1_out2_pa5 {
 };

 /omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ fdcan1_rx_pb8: fdcan1_rx_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ fdcan1_tx_pb9: fdcan1_tx_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c1_scl_pa13: i2c1_scl_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
  bias-pull-up;
  drive-open-drain;
 };

 /omit-if-no-ref/ i2c1_scl_pa15: i2c1_scl_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c1_scl_pb8: i2c1_scl_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c2_scl_pa9: i2c2_scl_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c2_scl_pc4: i2c2_scl_pc4 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_scl_pc8: i2c3_scl_pc8 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c1_sda_pa14: i2c1_sda_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c1_sda_pb7: i2c1_sda_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c1_sda_pb9: i2c1_sda_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c2_sda_pa8: i2c2_sda_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c2_sda_pf0: i2c2_sda_pf0 {
  pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_sda_pb5: i2c3_sda_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_sda_pc11: i2c3_sda_pc11 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c2_smba_pa10: i2c2_smba_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_smba_pa9: i2c3_smba_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2c3_smba_pb2: i2c3_smba_pb2 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_ck_pb13: i2s2_ck_pb13 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
  slew-rate = "very-high-speed";
 };

 /omit-if-no-ref/ i2s2_ck_pf1: i2s2_ck_pf1 {
  pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_ck_pb3: i2s3_ck_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_mck_pa8: i2s2_mck_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_mck_pa9: i2s3_mck_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_sd_pa11: i2s2_sd_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_sd_pb15: i2s2_sd_pb15 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_sd_pb5: i2s3_sd_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_sd_pc12: i2s3_sd_pc12 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s2_ws_pf0: i2s2_ws_pf0 {
  pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_ws_pa4: i2s3_ws_pa4 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sys_jtms_swdio_pa13: sys_jtms_swdio_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sys_jtck_swclk_pa14: sys_jtck_swclk_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sys_jtdi_pa15: sys_jtdi_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sys_jtdo_swo_pb3: sys_jtdo_swo_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sys_jtrst_pb4: sys_jtrst_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_out_pa14: lptim1_out_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_out_pb2: lptim1_out_pb2 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_in1_pb5: lptim1_in1_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0xb) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_etr_pb6: lptim1_etr_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0xb) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_in2_pb7: lptim1_in2_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0xb) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_in1_pc0: lptim1_in1_pc0 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_out_pc1: lptim1_out_pc1 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_in2_pc2: lptim1_in2_pc2 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lptim1_etr_pc3: lptim1_etr_pc3 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ opamp1_vinp_pa1: opamp1_vinp_pa1 {
 };

 /omit-if-no-ref/ opamp1_vout_pa2: opamp1_vout_pa2 {
 };

 /omit-if-no-ref/ opamp1_vinm_pa3: opamp1_vinm_pa3 {
 };

 /omit-if-no-ref/ opamp1_vinp_pa3: opamp1_vinp_pa3 {
 };

 /omit-if-no-ref/ opamp1_vinp_pa7: opamp1_vinp_pa7 {
 };

 /omit-if-no-ref/ opamp1_vinm_pc5: opamp1_vinm_pc5 {
 };

 /omit-if-no-ref/ opamp2_vinm_pa5: opamp2_vinm_pa5 {
 };

 /omit-if-no-ref/ opamp2_vout_pa6: opamp2_vout_pa6 {
 };

 /omit-if-no-ref/ opamp2_vinp_pa7: opamp2_vinp_pa7 {
 };

 /omit-if-no-ref/ opamp2_vinp_pb0: opamp2_vinp_pb0 {
 };

 /omit-if-no-ref/ opamp2_vinp_pb14: opamp2_vinp_pb14 {
 };

 /omit-if-no-ref/ opamp2_vinm_pc5: opamp2_vinm_pc5 {
 };

 /omit-if-no-ref/ opamp3_vinp_pa1: opamp3_vinp_pa1 {
 };

 /omit-if-no-ref/ opamp3_vinp_pb0: opamp3_vinp_pb0 {
 };

 /omit-if-no-ref/ opamp3_vout_pb1: opamp3_vout_pb1 {
 };

 /omit-if-no-ref/ opamp3_vinm_pb2: opamp3_vinm_pb2 {
 };

 /omit-if-no-ref/ opamp3_vinm_pb10: opamp3_vinm_pb10 {
 };

 /omit-if-no-ref/ opamp3_vinp_pb13: opamp3_vinp_pb13 {
 };

 /omit-if-no-ref/ rcc_mco_pa8: rcc_mco_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ rcc_mco_pg10: rcc_mco_pg10 {
  pinmux = <((((('G') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x0) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_ck1_pa3: sai1_ck1_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_mclk_a_pa3: sai1_mclk_a_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0xd) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_fs_b_pa4: sai1_fs_b_pa4 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0xd) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_ck2_pa8: sai1_ck2_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sck_a_pa8: sai1_sck_a_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_fs_a_pa9: sai1_fs_a_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_d1_pa10: sai1_d1_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sd_a_pa10: sai1_sd_a_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sd_b_pa13: sai1_sd_b_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0xd) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_fs_b_pa14: sai1_fs_b_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0xd) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sck_b_pb3: sai1_sck_b_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_mclk_b_pb4: sai1_mclk_b_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sd_b_pb5: sai1_sd_b_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_fs_b_pb6: sai1_fs_b_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_ck1_pb8: sai1_ck1_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_mclk_a_pb8: sai1_mclk_a_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_d2_pb9: sai1_d2_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_fs_a_pb9: sai1_fs_a_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sck_a_pb10: sai1_sck_a_pb10 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sd_a_pc1: sai1_sd_a_pc1 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0xd) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_d1_pc3: sai1_d1_pc3 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_sd_a_pc3: sai1_sd_a_pc3 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0xd) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ sai1_d3_pc5: sai1_d3_pc5 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
  bias-pull-down;
 };

 /omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi2_miso_pa10: spi2_miso_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi2_miso_pb14: spi2_miso_pb14 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi2_mosi_pa11: spi2_mosi_pa11 {
 };

 /omit-if-no-ref/ spi2_mosi_pb15: spi2_mosi_pb15 {
 };

 /omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
 };

 /omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
 };

 /omit-if-no-ref/ spi1_nss_pa4: spi1_nss_pa4 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
 };

 /omit-if-no-ref/ spi2_nss_pf0: spi2_nss_pf0 {
 };

 /omit-if-no-ref/ spi3_nss_pa4: spi3_nss_pa4 {
 };

 /omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
 };

 /omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi1_sck_pb3: spi1_sck_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ spi2_sck_pb13: spi2_sck_pb13 {
 };

 /omit-if-no-ref/ spi2_sck_pf1: spi2_sck_pf1 {
 };

 /omit-if-no-ref/ spi3_sck_pb3: spi3_sck_pb3 {
 };

 /omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
 };

 /omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin2_pa11: tim1_bkin2_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin_pa14: tim1_bkin_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin_pa15: tim1_bkin_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin_pb8: tim1_bkin_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin_pb10: tim1_bkin_pb10 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin2_pc3: tim1_bkin2_pc3 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_bkin_pc13: tim1_bkin_pc13 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_bkin_pa9: tim15_bkin_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_bkin_pc5: tim15_bkin_pc5 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_bkin_pb5: tim16_bkin_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim17_bkin_pa10: tim17_bkin_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim17_bkin_pb4: tim17_bkin_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin_pa0: tim8_bkin_pa0 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin_pa6: tim8_bkin_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin_pa10: tim8_bkin_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0xb) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin2_pb6: tim8_bkin2_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin_pb7: tim8_bkin_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin2_pc9: tim8_bkin2_pc9 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_bkin_pd2: tim8_bkin_pd2 {
  pinmux = <((((('D') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch1n_pa11: tim1_ch1n_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0xb) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch2n_pa12: tim1_ch2n_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch2n_pb0: tim1_ch2n_pb0 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch3n_pb9: tim1_ch3n_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch1n_pb13: tim1_ch1n_pb13 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch2n_pb14: tim1_ch2n_pb14 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch3n_pb15: tim1_ch3n_pb15 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch1_pc0: tim1_ch1_pc0 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch2_pc1: tim1_ch2_pc1 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch3_pc2: tim1_ch3_pc2 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch4_pc3: tim1_ch4_pc3 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch4n_pc5: tim1_ch4n_pc5 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch1n_pc13: tim1_ch1n_pc13 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim1_ch3n_pf0: tim1_ch3n_pf0 {
  pinmux = <((((('F') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch4_pa3: tim2_ch4_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch3_pa9: tim2_ch3_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch4_pa10: tim2_ch4_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch2_pb3: tim2_ch2_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch2_pa4: tim3_ch2_pa4 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch3_pb0: tim3_ch3_pb0 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch4_pb7: tim3_ch4_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch1_pa11: tim4_ch1_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch2_pa12: tim4_ch2_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch3_pa13: tim4_ch3_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch1_pb6: tim4_ch1_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch2_pb7: tim4_ch2_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch3_pb8: tim4_ch3_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim4_ch4_pb9: tim4_ch4_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_ch2_pa3: tim15_ch2_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x9) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_ch1_pb14: tim15_ch1_pb14 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_ch1n_pb15: tim15_ch1n_pb15 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim15_ch2_pb15: tim15_ch2_pb15 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_ch1_pa6: tim16_ch1_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_ch1_pa12: tim16_ch1_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_ch1n_pa13: tim16_ch1n_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_ch1_pb4: tim16_ch1_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_ch1n_pb6: tim16_ch1n_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim16_ch1_pb8: tim16_ch1_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim17_ch1_pa7: tim17_ch1_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim17_ch1_pb5: tim17_ch1_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim17_ch1n_pb7: tim17_ch1n_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim17_ch1_pb9: tim17_ch1_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x1) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch1n_pa7: tim8_ch1n_pa7 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch2_pa14: tim8_ch2_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch1_pa15: tim8_ch1_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x2) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch2n_pb0: tim8_ch2n_pb0 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch3n_pb1: tim8_ch3n_pb1 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch1n_pb3: tim8_ch1n_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch2n_pb4: tim8_ch2n_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch3n_pb5: tim8_ch3n_pb5 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x3) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch1_pb6: tim8_ch1_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch2_pb8: tim8_ch2_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch3_pb9: tim8_ch3_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0xa) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch1_pc6: tim8_ch1_pc6 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch2_pc7: tim8_ch2_pc7 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch3_pc8: tim8_ch3_pc8 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch4_pc9: tim8_ch4_pc9 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch1n_pc10: tim8_ch1n_pc10 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch2n_pc11: tim8_ch2n_pc11 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch3n_pc12: tim8_ch3n_pc12 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x4) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ tim8_ch4n_pc13: tim8_ch4n_pc13 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x6) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_cts_pa6: lpuart1_cts_pa6 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_cts_pb13: lpuart1_cts_pb13 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_cts_pa13: usart3_cts_pa13 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_cts_pb13: usart3_cts_pb13 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((13) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ uart4_cts_pb7: uart4_cts_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0xe) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_de_pa12: usart1_de_pa12 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
  drive-push-pull;
 };

 /omit-if-no-ref/ lpuart1_de_pb1: lpuart1_de_pb1 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_de_pb12: lpuart1_de_pb12 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((12) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_de_pa1: usart2_de_pa1 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_de_pb14: usart3_de_pb14 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
 };

 /omit-if-no-ref/ lpuart1_rts_pb1: lpuart1_rts_pb1 {
 };

 /omit-if-no-ref/ lpuart1_rts_pb12: lpuart1_rts_pb12 {
 };

 /omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
 };

 /omit-if-no-ref/ usart3_rts_pb14: usart3_rts_pb14 {
 };

 /omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
 };

 /omit-if-no-ref/ lpuart1_rx_pa3: lpuart1_rx_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_rx_pb7: usart1_rx_pb7 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((7) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_rx_pb10: lpuart1_rx_pb10 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_rx_pc0: lpuart1_rx_pc0 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((0) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_rx_pc5: usart1_rx_pc5 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((5) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_rx_pa3: usart2_rx_pa3 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_rx_pa15: usart2_rx_pa15 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((15) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_rx_pb4: usart2_rx_pb4 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_rx_pb8: usart3_rx_pb8 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((8) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_tx_pa2: lpuart1_tx_pa2 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0xc) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_tx_pb6: usart1_tx_pb6 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((6) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_tx_pb11: lpuart1_tx_pb11 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((11) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ lpuart1_tx_pc1: lpuart1_tx_pc1 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((1) & 0xFU) << 5U) | (((0x8) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart1_tx_pc4: usart1_tx_pc4 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((4) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((2) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_tx_pa14: usart2_tx_pa14 {
  pinmux = <((((('A') - 'A') & 0x1FU) << 9U) | (((14) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart2_tx_pb3: usart2_tx_pb3 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((3) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_tx_pb9: usart3_tx_pb9 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((9) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
  pinmux = <((((('B') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x7) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
  pinmux = <((((('C') - 'A') & 0x1FU) << 9U) | (((10) & 0xFU) << 5U) | (((0x5) & 0x1FU) << 0U))>;
 };

 /omit-if-no-ref/ ucpd1_cc2_pb4: ucpd1_cc2_pb4 {
 };

 /omit-if-no-ref/ ucpd1_cc1_pb6: ucpd1_cc1_pb6 {
 };

 /omit-if-no-ref/ usb_dm_pa11: usb_dm_pa11 {
 };

 /omit-if-no-ref/ usb_dp_pa12: usb_dp_pa12 {
 };

};
# 10 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts" 2
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi" 1

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/gpio/arduino-header-r3.h" 1 3 4
# 8 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi" 2

/ {
 arduino_header: connector {
  compatible = "arduino-header-r3";
  #gpio-cells = <2>;
  gpio-map-mask = <0xffffffff 0xffffffc0>;
  gpio-map-pass-thru = <0 0x3f>;
  gpio-map = <0 0 &gpioa 0 0>,
      <1 0 &gpioa 1 0>,
      <2 0 &gpioa 4 0>,
      <3 0 &gpiob 0 0>,
      <4 0 &gpioc 1 0>,
      <5 0 &gpioc 0 0>,
      <6 0 &gpioc 5 0>,
      <7 0 &gpioc 4 0>,
      <8 0 &gpioa 10 0>,
      <9 0 &gpiob 3 0>,
      <10 0 &gpiob 5 0>,
      <11 0 &gpiob 4 0>,
      <12 0 &gpiob 10 0>,
      <13 0 &gpioa 8 0>,
      <14 0 &gpioa 9 0>,
      <15 0 &gpioc 7 0>,
      <16 0 &gpiob 6 0>,
      <17 0 &gpioa 7 0>,
      <18 0 &gpioa 6 0>,
      <19 0 &gpioa 5 0>,
      <20 0 &gpiob 9 0>,
      <21 0 &gpiob 8 0>;
 };
};

arduino_i2c: &i2c1 {};

arduino_spi: &spi1 {};

arduino_serial: &usart1 {};
# 11 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts" 2
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi" 1

# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/gpio/st-morpho-header.h" 1 3 4
# 8 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/st_morpho_connector.dtsi" 2

/ {
 st_morpho_header: st-morpho-header {
  compatible = "st-morpho-header";
  gpio-map-mask = <0xFF 0x0>;
  gpio-map-pass-thru = <0x0 0x7F>;
  gpio-map = <0 0 &gpioc 10 0>,
      <1 0 &gpioc 11 0>,
      <2 0 &gpioc 12 0>,
      <3 0 &gpiod 2 0>,
      <12 0 &gpioa 13 0>,
      <14 0 &gpioa 14 0>,
      <16 0 &gpioa 15 0>,
      <20 0 &gpiob 7 0>,
      <22 0 &gpioc 13 0>,
      <24 0 &gpioc 14 0>,
      <26 0 &gpioc 15 0>,
      <27 0 &gpioa 0 0>,
      <28 0 &gpiof 0 0>,
      <29 0 &gpioa 1 0>,
      <30 0 &gpiof 1 0>,
      <31 0 &gpioa 4 0>,
      <33 0 &gpiob 0 0>,
      <34 0 &gpioc 2 0>,
      <35 0 &gpioc 1 0>,
      <36 0 &gpioc 3 0>,
      <37 0 &gpioc 0 0>,
      <72 0 &gpioc 9 0>,
      <73 0 &gpioc 8 0>,
      <74 0 &gpiob 8 0>,
      <75 0 &gpioc 6 0>,
      <76 0 &gpiob 9 0>,
      <77 0 &gpioc 5 0>,
      <82 0 &gpiob 13 0>,
      <83 0 &gpioa 12 0>,
      <84 0 &gpiob 14 0>,
      <85 0 &gpioa 11 0>,
      <86 0 &gpiob 15 0>,
      <87 0 &gpiob 12 0>,
      <88 0 &gpiob 6 0>,
      <89 0 &gpiob 11 0>,
      <90 0 &gpioc 7 0>,
      <92 0 &gpioa 9 0>,
      <93 0 &gpiob 2 0>,
      <94 0 &gpioa 8 0>,
      <95 0 &gpiob 1 0>,
      <96 0 &gpiob 10 0>,
      <97 0 &gpioa 7 0>,
      <98 0 &gpiob 4 0>,
      <99 0 &gpioa 6 0>,
      <100 0 &gpiob 5 0>,
      <101 0 &gpioa 5 0>,
      <102 0 &gpiob 3 0>,
      <104 0 &gpioa 10 0>,
      <105 0 &gpioc 4 0>,
      <106 0 &gpioa 2 0>,
      <108 0 &gpioa 3 0>;
 };
};
# 12 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts" 2
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h" 1 3 4
# 13 "/home/jeremy/utat-dev/zephyrproject/zephyr/boards/st/nucleo_g431rb/nucleo_g431rb.dts" 2

/ {
 model = "STMicroelectronics STM32G431RB-NUCLEO board";
 compatible = "st,stm32g431rb-nucleo";

 chosen {
  zephyr,console = &lpuart1;
  zephyr,shell-uart = &lpuart1;
  zephyr,sram = &sram0;
  zephyr,flash = &flash0;
  zephyr,code-partition = &slot0_partition;
 };

 leds: leds {
  compatible = "gpio-leds";

  green_led: led_0 {
   gpios = <&gpioa 5 (0 << 0)>;
   label = "User LD2";
  };
 };

 pwmleds {
  compatible = "pwm-leds";

  green_pwm_led: green_pwm_led {
   pwms = <&pwm2 1 (((20) * 1000UL) * 1000UL) (0 << 0)>;
  };
 };

 gpio_keys {
  compatible = "gpio-keys";

  user_button: button {
   label = "User";
   gpios = <&gpioc 13 (0 << 0)>;
   zephyr,code = <11>;
  };
 };

 aliases {
  led0 = &green_led;
  mcuboot-led0 = &green_led;
  pwm-led0 = &green_pwm_led;
  sw0 = &user_button;
  watchdog0 = &iwdg;
 };
};

&clk_lsi {
 status = "okay";
};

&clk_lse {
};

&clk_hsi48 {
};

&clk_hse {
 clock-frequency = <(((24) * 1000) * 1000)>;
};

&pll {
 div-m = <6>;
 mul-n = <85>;
 div-p = <7>;
 div-q = <2>;
 div-r = <2>;
 clocks = <&clk_hse>;
};

&rcc {
 clocks = <&pll>;
 clock-frequency = <(((170) * 1000) * 1000)>;
 ahb-prescaler = <1>;
 apb1-prescaler = <1>;
 apb2-prescaler = <1>;
};

&rng {
 clocks = <&rcc (0x04c) (1 << 26)>,
   <&rcc ((0x003 + 1) + 1) ((((0x88) & 0xFFFFU) << 0U) | (((26) & 0x1FU) << 16U) | ((((27) - (26)) & 0x3U) << 21U) | ((((0)) & 0xFFU) << 24U))>;
};

&usart1 {
 pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
 pinctrl-names = "default";
 current-speed = <115200>;
};

&lpuart1 {
 pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
};

&i2c1 {
 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
};

&spi1 {
 pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
 cs-gpios = <&gpiob 6 ((1 << 0) | (1 << 4))>;
};

&spi2 {
 pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
       &spi2_miso_pb14 &spi2_mosi_pb15>;
};

&spi3 {

 pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pc10
       &spi3_miso_pc11 &spi3_mosi_pc12>;
};

&timers2 {

 pwm2: pwm {
  status = "okay";
  pinctrl-0 = <&tim2_ch1_pa5>;
  pinctrl-names = "default";
 };
};

stm32_lp_tick_source: &lptim1 {
 clocks = <&rcc (0x058) (1 << 31)>,
   <&rcc 0x002 ((((0x88) & 0xFFFFU) << 0U) | (((18) & 0x1FU) << 16U) | ((((19) - (18)) & 0x3U) << 21U) | ((((3)) & 0xFFU) << 24U))>;
};

&rtc {
 clocks = <&rcc (0x058) (1 << 10)>,
   <&rcc 0x003 ((((0x90) & 0xFFFFU) << 0U) | (((8) & 0x1FU) << 16U) | ((((9) - (8)) & 0x3U) << 21U) | ((((2)) & 0xFFU) << 24U))>;
};

&flash0 {
 partitions {
  ranges;

  boot_partition: partition@0 {
   compatible = "zephyr,mapped-partition";
   label = "mcuboot";
   reg = <0x00000000 0x00008000>;
  };

  slot0_partition: partition@8800 {
   label = "image-0";
   reg = <0x00008000 0x00010000>;
  };

  slot1_partition: partition@14800 {
   label = "image-1";
   reg = <0x00010000 0x0018000>;
  };

  storage_partition: partition@1f000 {
   label = "storage";
   reg = <0x00018000 0x00020000>;
  };
 };
};

&iwdg {
};

&dac1 {
 pinctrl-0 = <&dac1_out1_pa4>;
};
# 0 "<command-line>" 2
# 1 "/home/jeremy/utat-dev/zephyrproject/bootloader/mcuboot/boot/zephyr/app.overlay" 1
/ {
 chosen {
  zephyr,code-partition = &boot_partition;
 };
};
# 1 "/home/jeremy/utat-dev/zephyrproject/zephyr/misc/empty_file.c"

Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).

The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.

For details, see "2.3.6 reg" in Devicetree Specification v0.4.

Indicates the operational status of the hardware or other
resource that the node represents. In particular:

  - "okay" means the resource is operational and, for example,
    can be used by device drivers
  - "disabled" means the resource is not operational and the system
    should treat it as if it is not present

For details, see "2.3.4 status" in Devicetree Specification v0.4.

This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.

The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.

The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.

For details, see "2.3.1 compatible" in Devicetree Specification v0.4.

Optional names given to each register block in the "reg" property.
For example:

  / {
       soc {
           #address-cells = <1>;
           #size-cells = <1>;

           uart@1000 {
               reg = <0x1000 0x2000>, <0x3000 0x4000>;
               reg-names = "foo", "bar";
           };
       };
  };

The uart@1000 node has two register blocks:

  - one with base address 0x1000, size 0x2000, and name "foo"
  - another with base address 0x3000, size 0x4000, and name "bar"

Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.

Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.

If present, this refers to the node which handles interrupts generated
by this device.

Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.

For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.

Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:

  https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

Optional names given to each clock provider in the "clocks" property.

This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree

This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.

Indicates that the device is capable of coherent DMA operations.

For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.

Optional names given to the DMA channel specifiers in the "dmas" property.

Optional names given to the IO channel specifiers in the "io-channels" property.

Optional names given to the mbox specifiers in the "mboxes" property.

Optional names given to the power domain specifiers in the "power-domains" property.

Optional names given to the hwlock specifiers in the "hwlocks" property.

Do not initialize device automatically on boot. Device should be manually
initialized using device_init().

Property to identify that a device can be used as wake up source.

When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.

Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.

Automatically configure the device for runtime power management after the
init function runs.

For ARM Cortex-M SysTick timer, the CLKSOURCE bit in the
SysTick Control and Status Register (CSR) selects the clock source.
If this property is present, the external reference clock is selected.
If absent, the processor/core clock is selected.

Expected names are the following:
- "adcx" for the enabling the register clock (mandatory)
- "adc_ker" for configuring the kernel clock (if applicable)
- "adc_pre" for configuring the prescaler (if applicable)
Kernel clock and prescaler may be shared between several ADC instances.
In that case, the same kernel clock/prescaler Device Tree configuration
must be used on all instances that share the kernel clock/prescaler
to avoid conflicts.

Type of ADC clock source :
- "SYNC": derived from the bus clock.
- "ASYNC" : independent and asynchronous with the bus clock
One of the two values may not apply to some series. Refer to the RefMan.
If an asynchronous clock is selected, a kernel clock in the "clocks" property
has to be defined explicitly.

Clock prescaler at the input of the ADC:
Apply to synchronous or asynchronous clock depending on the STM32
st,adc-clock-source.
Some of the values may not apply to some series, and may depend on the
selected clock source. Refer to the RefMan.
On STM32F3x, this configures only the synchronous prescaler
(use the "clocks" property to set asynchronous prescaler).

Indicates the reference voltage of the ADC in mV (on the target board).

List of the resolutions supported by the ADC instance.
By convention, they should be listed in descending order (e.g. <12 10 8 6>).

List all the sampling times supported by the ADC instance.
Rounded up if needed. Order is important: their index matches their binary
value in the register.

Number of sampling time common channels for this ADC instance, if any.

Type of ADC sequencer:
- "fixed": Channels of a sequence are sampled from lowest to highest.
- "programmable": Channels of a sequence can be sampled in any order.

Type of ADC oversampler:
- "none": No oversampler
- "minimal": Oversampler with 8 possible oversampling values (2, 4, 8, ..., 256)
- "extended": Oversampler with 1024 possible oversampling values (1..1024)

Presence and type of ADC internal regulator if any.
- "none": No internal regulator.
- "startup-sw-delay": Internal regulator is present and its startup time is checked with a
  software delay.
- "startup-hw-status": Internal regulator is present and its startup time is checked with a
  status flag in a register.

If present, it indicates that the ADC instance has a deep power down feature.

If present, it indicates that the ADC instance has a channel preselection register.

If present, it indicates that the ADC instance supports differential channel inputs.

If present, it indicates that the ADC instance supports the injected channel feature.

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

Names for the provided states. The number of names needs to match the
number of states.

Channel configuration.

All nodes using this binding must be named "channel", otherwise their
data will not be accessible for the ADC API macros.

This is based on Linux, documentation:
  https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/adc/adc.yaml

Gain selection:
- ADC_GAIN_1_6: x 1/6
- ADC_GAIN_1_5: x 1/5
- ADC_GAIN_1_4: x 1/4
- ADC_GAIN_2_7: x 2/7
- ADC_GAIN_1_3: x 1/3
- ADC_GAIN_2_5: x 2/5
- ADC_GAIN_1_2: x 1/2
- ADC_GAIN_2_3: x 2/3
- ADC_GAIN_4_5: x 4/5
- ADC_GAIN_1:   x 1
- ADC_GAIN_2:   x 2
- ADC_GAIN_3:   x 3
- ADC_GAIN_4:   x 4
- ADC_GAIN_6:   x 6
- ADC_GAIN_8:   x 8
- ADC_GAIN_12:  x 12
- ADC_GAIN_16:  x 16
- ADC_GAIN_24:  x 24
- ADC_GAIN_32:  x 32
- ADC_GAIN_64:  x 64
- ADC_GAIN_128: x 128

Reference selection:
- ADC_REF_VDD_1:     VDD
- ADC_REF_VDD_1_2:   VDD/2
- ADC_REF_VDD_1_3:   VDD/3
- ADC_REF_VDD_1_4:   VDD/4
- ADC_REF_INTERNAL:  Internal
- ADC_REF_EXTERNAL0: External, input 0
- ADC_REF_EXTERNAL1: External, input 1

This property can be used to specify the voltage (in millivolts)
of the reference selected for this channel, so that applications
can get that value if needed for some calculations.
For the internal reference, the voltage can be usually obtained with
a dedicated ADC API call, so there is no need to use this property
in that case, but for other references this property can be useful.

Acquisition time.
Use the ADC_ACQ_TIME macro to compose the value for this property
or pass ADC_ACQ_TIME_DEFAULT to use the default setting for a given
hardware (e.g. when the hardware does not allow to configure the
acquisition time).

When set, selects differential input mode for the channel. Otherwise,
single-ended mode is used unless the zephyr,input-negative property is
specified, in which case the differential mode is selected implicitly.

Positive ADC input. Used only for drivers that select
the ADC_CONFIGURABLE_INPUTS Kconfig option.

Negative ADC input. Used only for drivers that select
When specified, implies the differential input mode for the channel.

Oversampling setting to be used for the channel.
When specified, each sample is averaged from 2^N conversion results
(where N is the provided value).

Output pin selection for the current sources. The actual
interpretation depends on the driver. This is used only for drivers
which select the ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN
Kconfig option.

Output pin selection for the bias voltage. The actual interpretation
depends on the driver. This is used only for drivers which select
the ADC_CONFIGURABLE_VBIAS_PIN Kconfig option.

STM32 RCC (Reset and Clock controller).

This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.

Configuring STM32 Reset and Clock controller node:

System clock source should be selected amongst the clock nodes available in "clocks"
node (typically 'clk_hse, clk_hsi', 'pll', ...).
Core clock frequency should also be defined, using "clock-frequency" property.
Note:
        Core clock frequency  = SYSCLK / AHB prescaler
Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
prescaler properties.
Here is an example of correctly configured rcc node:
&rcc {
         clocks = <&pll>;  /* Select 80MHz pll as SYSCLK source */
         ahb-prescaler = <2>;
         clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
         apb1-prescaler = <1>;
         apb2-prescaler = <1>;
}

Specifying a gated clock:

To specify a gated clock, a peripheral should define a "clocks" property such as:
... {
         ...
         clocks = <&rcc STM32_CLOCK(APB2, 5)>;
         ...
}

After the phandle referring to rcc node, use the STM32_CLOCK() macro which accepts
two parameters: the first specifies the bus on which the peripheral is attached, and
the second indicates the bit number controlling the peripheral clock gate in that
bus's control register in RCC. As an example, the snippet above indicates that the
peripheral gate is controlled by bit 5 in RCC_APB2ENR (USART6EN on STM32F401).
The gated clock is required when accessing to the peripheral controller is needed
(generally for configuring the device). If dual clock domain is not used, it is
also used for peripheral operation.

Note: in situations where more than one bit is required, use the explicit form:
... {
         ...
         clocks = <&rcc STM32_CLOCK_BUS_APB2 ((1 << 14) | (1 << 7))>;
         ...
}
where 14 and 7 are the bits that control the peripheral clock gate.
(You can have more than two bits, and they do not have to be contiguous).

Specifying a domain clock source:

Specifying a domain source clock could be done by adding a clock specifier to the
clock property:
... {
         ...
         clocks = <&rcc STM32_CLOCK(APB2, 5)>,
                      <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
         ...
}
In this example, I2C1 device is assigned HSI as domain clock source.
Domain clock is independent from the bus/gated clock and allows access to the device's
register while the gated clock is off. As it doesn't feed the peripheral's controller, it
allows peripheral operation, but can't be used for peripheral configuration.
It is peripheral driver's responsibility to query and use clock source information in
accordance with clock_control API specifications.

Since the peripheral subsystem rate is dictated by the clock used for peripheral
operation, same clock should be used in calls to `clock_control_get_rate()`

Note 1: No additional specifier means gating clock is also the clock source (ie
        'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
        cell to explicitly set it.
Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
        should be the one matching SoC reset state. Confere reference manual to check
        what is the reset value of the clock source for each peripheral.

Specifying a divided domain clock source:

Some peripherals are sourced through fixed clock dividers. For such cases there is
STM32_CLOCK_DIV() macro, which allows to specify such divider value. Selecting HSE/2 (HSE
frequency divided by 2) is done with following clock property:
... {
         ...
         clocks = <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
         ...
}

AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.

On some parts, it could be required to set up highest core frequencies
(>80MHz) in two steps in order to prevent undershoot.
This is done by applying an intermediate AHB prescaler before switching
System Clock source to PLL. Once done, prescaler is set back to expected
value.

STM32G4 main PLL.

It can take one of clk_hse or clk_hsi as input clock, with
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
clock in this acceptable range.

PLL can have up to 3 output clocks and for each output clock, the
frequency can be computed with the following formulae:

  f(PLL_P) = f(VCO clock) / PLLP  --> to ADC
  f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48MCLK (for USB, RNG)
  f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)

    with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

The PLL output frequency must not exceed 170 MHz.

Division factor after PLLSAI2_R for LTDC pixel clock. Only available
on PLLSAI2 of STM32L4+ series. If available, this property must be
provided when PLLSAI2_R is enabled (i.e., if `div-r` is provided).

HSE crystal oscillator bypass
Set to the property to by-pass the oscillator with an external clock.

HSE clock security system enabled
Set the property to enable the clock security system (CSS) for the HSE clock.

If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled,
a clock failure event is sent to timers, and a non-maskable interrupt is generated to
inform the software about the failure, allowing the MCU to perform rescue operations.
See the MCU reference manual for details.

The interaction of CSS and low-power modes is unclear from the documentation.
For at least some devices Zephyr will reconfigure the clocks on resuming from low-power
modes; this will include re-enabling CSS. However it is important that you verify
this for your own hardware.

data will not be accessible for the DAC API macros.

This binding gives a base representation of the STM32 pins configuration

Reused from
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
Integer represents gpio pin number and mux setting.
Each integer encodes a port, line and alternate function.
With:
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
- function: The function number, can be:
* 0 : Alternate Function 0
* 1 : Alternate Function 1
* 2 : Alternate Function 2
* ...
* 15 : Alternate Function 15
* 16 : Analog
* 17 : GPIO
In case selected pin function is GPIO, pin is statically configured as
a plain input/output GPIO. Default configuration is input. Output value
can be configured by adding 'ouptut-low' or 'output-high' properties
to the pin configuration.

To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
  -include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h
Some examples of macro usage:
   GPIO A9 set as alternate function 2
... {
         pinmux = <STM32_PINMUX('A', 9, AF2)>;
};
   GPIO A9 set as analog
... {
         pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
   GPIO A9 set as GPIO output high
... {
         pinmux = <STM32_PINMUX('A', 9, GPIO)>;
         output-high;
};

Pin speed. Default to low-speed. For few pins (PA11 and
PB3 depending on SoCs)hardware reset value could differ
(very-high-speed). Carefully check reference manual for these pins.

This property provides a byte which should used to enable non-permanent
readout protection (RDP1). Actually, any byte except 0xAA and 0xCC
(which are used by RDP0 and RDP2 respectively) can be used to enable
RDP1 but in multi-image environment, some other image could check if
RDP1 is enabled by comparing it to some hardcoded value. The byte has to
be different than 0xAA and 0xCC.

STM32 flash memory.

This binding is for the flash memory itself, not the flash controller peripheral.
For that, see the "st,stm32-flash-controller" binding.

max erase time(millisecond) of a flash sector or page or half-page

Embedded flash memory bank 2 size in KBytes.
Used by CM4 CPU because it cannot access flash controller register to read size.
Provides a way to configure this size when the flash controller driver runs on CM4 CPU.

Memory-mapped partition of a flash (or other non-volatile storage) memory.

The `zephyr,mapped-partition` node should be (descendant) children of the NVM memory node, either
directly or through intermediatory grouping child nodes or through parent
`zephyr,mapped-partition` nodes. Note that the NVM memory node and NVM controller nodes must have
`ranges` properties to indicate that they are all part of the SoC's address space which specify
the full range of the NVM area (usually the same as the `reg` property with a 0x0 prepended
before the offset value). Nested `zephyr,mapped-partition` nodes are supported, and should have
`ranges` properties set to indicate their range to their child nodes.

Number of cells required to represent a child node's reg property address. This must be
large enough to represent the start offset of each partition.

large enough to represent the size of each partition in bytes.

This should be in the format <OFFSET SIZE>, where OFFSET is the offset of the flash
partition relative to the base address of the parent memory, and SIZE is the size of the
partition in bytes.

/*
 * The NVM controller node defines the ranges which map the NVM memory nodes to the CPU address
 * space.
 */
flash_controller: flash-controller@4001e000 {
        compatible = "vnd,flash-controller"
        reg = <0x4001e000 0x1000>
        ranges;
        #address-cells = <1>;
        #size-cells = <1>;

        /*
         * An NVM memory node describes a consecutive block of non volatile physical memory.
         * Partitions are added to the this node, adhering to physical limitations like
         * write-block-size. An empty `ranges;` property is required to ensure any partition
         * added to the NVM memory is mapped correctly to the CPU address space, and a
         * nodelabel should be defined make it easier for applications to add add partitions
         * to the NVM memory node.
         */
        flash0: flash@0 {
                compatible = "soc-nv-flash"
                reg = <0x0 DT_SIZE_K(1024)>;
                ranges = <0x0 0x0 DT_SIZE_K(1024)>
                #address-cells = <1>;
                #size-cells = <1>;

                /*
                 * The 'partitions' grouping is optional, it allows for clearing all partitions
                 * in a device (e.g. using a dtc overlay file) but is not required. If used,
                 * then it needs a `ranges;` property and to specify the #address-cells and
                 * #size-cells properties
                 */
                partitions {
                        ranges;
                        #address-cells = <1>;
                        #size-cells = <1>;

                        /*
                         * Offsets are relative to the flash0 node, if flash0 had an address of
                         * 0x10000000 then the below offset of 0x0 means address 0x10000000
                         */
                        boot_partition: partition@0 {
                                compatible = "zephyr,mapped-partition";
                                label = "mcuboot";
                                reg = <0x0 0xc000>;
                        };

                        slot0_partition: partition@c000 {
                                label = "image-0";
                                reg = <0xc000 0x76000>;
                        };

                        slot1_partition: partition@82000 {
                                label = "image-1";
                                reg = <0x82000 0x76000>;
                        };

                        /*
                         * Below example disables an NVM partition, if using the flash map
                         * subsystem with the default mappings then the below partition will
                         * not be present in the flash map
                         */
                        storage_partition: partition@f8000 {
                                label = "storage";
                                reg = <0xf8000 0x8000>;
                                status = "disabled";
                         };
                };
        };

        flash1: flash@10000000 {
                reg = <0x10000000 DT_SIZE_K(256)>;
                ranges = <0x0 0x10000000 DT_SIZE_K(256)>;

                /*
                 * Below demonstrates usage without partitions {}; grouping, and demos
                 * partitions inside of a parent partition
                 */
                external_partition: partition@0 {
                        compatible = "zephyr,mapped-partition";
                        reg = <0x0 0x10000>;
                        ranges = <0x0 0x0 0x10000>;

                        external_inner_a_partition: partition@0 {
                                reg = <0x0 0x6000>;
                        };

                        external_inner_b_partition: partition@6000 {
                                reg = <0x6000 0xa000>;
                        };
                };
        };
};

The NVM embedded in STM32 SoCs contains One-Time-Programmable regions
in addition to the "regular" region which can be programmed at will.
The OTP regions are usually provisioned by STMicroelectronics during
manufacturing (which makes them read-only areas). Some products also
provide an "OTP for user data" area which can be written in the field.

Refer to your product's Reference Manual and Data Sheet for more details.

Start address and size of NVM OTP area

Note: for User OTP area nodes, "locking bits" that may be found at the end
of the OTP area must not be included in the `size` part of this property.

Number of cells required to represent a child node's
reg property address.

Each child node of the NVMEM provider node represents
an individual NVMEM cell. These should usually
look like this:

  cell_nodelabel: cell@START_OFFSET {
          reg = <0xSTART_OFFSET 0xSIZE>;
          #nvmem-cell-cells = <0>;
  };

This should be in the format <OFFSET SIZE>, where OFFSET
is the offset of the NVMEM cell relative to the base
address of the parent memory, and SIZE is the size of
the cell in bytes.

STM32 Reset and Clock Control (RCC) Controller.

This node is in charge of reset control for AHB (Advanced High Performance)
and APB (Advanced Peripheral) bus domains.

To specify the reset line in a peripheral, the standard resets property needs
to be used, e.g.:

  usart1: serial@xxx {
      ...
      /* Cell contains information about RCU register offset and bit */
      resets = <&rctl STM32_RESET(ABP2, 4)>;
      ...
  };

RCC reset cells are available in
include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.

Number of cells in reset property. There must be a cell
named "id" to use the reset_dt_spec macros.

Indicates if the driver should set bit in clear register to
deassert reset.

Total number of EXTI lines dedicated to GPIO interrupts.
The default value of 16 mirrors hardware of most STM32 devices.

Description of the input lines range for each interrupt line supported
by the external interrupt controller. For each line a couple of integers is
provided: the number of the first line of the range start and the length
of the range.
As example:
       line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
                     <4 1>, <5 5>, <10 6>;
Above property provides event-range for 7 lines.
5 first lines contain one element
6th line starts with input line 5 and contains 5 elements (5 to 9)
7th line starts with inupt line 10 and contains 6 elements (10 to 15)

STM32 Pin controller.

Based on pincfg-node.yaml binding.

Note: `bias-disable` and `drive-push-pull` are default pin configurations.
       They will be applied in case no `bias-foo` or `driver-bar` properties
       are set.

Remaps the PA11 pin to operate as PA9 pin. Use of this property is restricted to STM32G0 and STM32C0 SoCs.

Remaps the PA12 pin to operate as PA10 pin. Use of this property is restricted to STM32G0 and STM32C0 SoCs.

Remaps the PA11/PA12 pin to operate as PA9/PA10 pin. Use of this property is restricted to STM32F070x SoCs.

This property indicates the number of in-use slots of available slots
for GPIOs. The STM32 GPIO controller typically has all 16 possible port
IO with few exceptions. It should only be necessary to explicitly set
this property if the controller itself does not implement all 16 port
IO register bits; for example PORTE in the STM32WB55xx series which only
implements the first 5. Package restrictions on the number of exposed
GPIO should not influence this property. For cases in which there might
be holes in the slot range, this value should be the max slot number+1.

If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
this property contains an additional set of tuples which specify which GPIOs
are unusable. This property indicates the start and size of the GPIOs
that can't be used.

For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.

This is an array of strings defining the names of the GPIO lines
going out of the GPIO controller

Optional GPIO hog configuration.

Each GPIO controller may contain GPIO hog definitions. GPIO hogging is a mechanism for
providing automatic GPIO configuration during driver initialization when Kconfig
CONFIG_GPIO_HOGS is enabled.

Each GPIO hog is represented as a child node of the GPIO controller.

Example:
  &gpio1 {
    mux-hog {
      gpio-hog;
      gpios = <10 GPIO_ACTIVE_HIGH>, <11 GPIO_ACTIVE_HIGH>;
      output-high;
    };
  };

  &gpio2 {
    test-hog {
      gpio-hog;
      gpios = <26 GPIO_ACTIVE_HIGH>;
      output-low;
      line-name = "test";
  };
};

This is an array of GPIO specifiers (e.g. pin, flags) to be hogged. The number of array
entries must be an integer multiple of the number of GPIO specifier cells for the parent
GPIO controller.

If this property is set, the GPIO is configured as an input. This property takes
precedence over the output-low and output-high properties.

If this property is set, the GPIO is configured as an output set to logical low. This
property takes precedence over the output-high property.

If this property is set, the GPIO is configured as an output set to logical high.

Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.

Sets the number of stop bits. Defaults to standard of 1 if not specified.

Sets the number of data bits. Defaults to standard of 8 if not specified.

Enable the single wire half-duplex communication.
Using this mode, TX and RX lines are internally connected and
only TX pin is used afterwards and should be configured.
RX/TX conflicts must be handled on user side.

Swap the TX and RX pins. Used in case of a cross wired connection.

EXTI line number matching the device wakeup interrupt mask register.
This property is required on stm32 devices where the wakeup interrupt signal could be
configured masked at boot (sm32wl55 for instance), preventing the device to wakeup
the core from stop mode(s).
Valid range: 0 - 31

Enable activating an external transeiver through the DE pin which must also be configured
using pinctrl.

Defines the time between the activation of the DE signal and the beginning of the start bit.
It is expressed in 16th of a bit time.

Defines the time between the end of the stop bit and the deactivation of the DE signal.

Invert the binary logic of the de pin. When enabled, physical logic levels are inverted and
we use 1=Low, 0=High instead of 1=High, 0=Low.

Enables transmit and receive FIFO using default FIFO configuration (typically threshold is
set to 1/8).
In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also
allows more reliable communication with UART devices sensitive to variation of inter-frames
delays.
In RX, FIFO reduces overrun occurrences.

Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity, 3 for mark parity and 4 for space parity.
Default to none if not specified.

Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and

Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and

An optional table of pre-computed i2c timing values with the
matching clock configuration.

Precise timings values for a given Hardware can be pre-computed
with a tool like STM32CubeMX or directly from I2C_TIMINGR register
description.

Because timing value is valid for a given I2C peripheral clock
frequency and target I2C bus clock, each timing value must be
provided with the matching configuration.

The resulting table entries should look like <periph_clock
clock-frequency timing>

For example timings could be defined as

    timings = <64000000 I2C_BITRATE_STANDARD 0x10707DBC>,
              <64000000 I2C_BITRATE_FAST 0x00603D56>,
              <56000000 I2C_BITRATE_STANDARD 0x10606DA4>,
              <56000000 I2C_BITRATE_FAST 0x00501D63>;

GPIO to which the I2C SCL signal is routed. This is only needed for
I2C bus recovery support.

GPIO to which the I2C SDA signal is routed. This is only needed for

Optional DMA channels used by the I2C peripheral. If specified, these
channels can be used to handle RX and TX transactions over DMA.

Names of the optional DMA channels. Expected values are "tx" for
the TX channel and "rx" for the RX channel.

Indicates the data width supported by the SPI instance.
- full-4-to-32-bit: supports data width from 4 to 32 bits
- full-4-to-16-bit: supports data width from 4 to 16 bits
- limited-8-16-bit: supports only 8 and 16-bit data widths

Force operation in "Soft NSS" mode without CS/NSS pin.

This is useful in situations where the SPI interface
is connected to a single controller or peripheral and
does not require CS/NSS for proper operation.

This property is overridden by the `cs-gpios` property:
if provided, SPI instance also operates in "Soft NSS"
mode, but GPIO CS pins are used during transactions.

If neither this property nor `cs-gpios` are provided,
the SPI instance operates in "Hard NSS" mode.

An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.

STM32 Controller Area Network (CAN) controller with Flexible Data (FD) rate and fixed message RAM
layout.

FDCAN kernel/domain clock divider. The resulting clock is fed to the FDCAN time quanta
clock. Note that the divisor is common to all 'st,stm32-fdcan' instances.

The clock divider, which is set via the FDCAN_CKDIV register, defaults to divide by 1 unless
this property is provided.

Phandle to the counter device to be used as the external RX timestamp source.

When this property is defined, the driver configures the FDCAN Timestamp
Counter Configuration (TSCC) to use the External Timestamp (TSS=0x2).

Hardware Constraint: The selected timer must be physically routed to the
fdcan_ts input in the SoC interconnect. (e.g. TIM3 on STM32G4). The exact timer
connected to the fdcan_ts input can be found in the reference manual of the specific SoC.

Bosch M_CAN message RAM configuration. The cells in the array have the following format:

<offset std-filter-elements ext-filter-elements rx-fifo0-elements rx-fifo1-elements
rx-buffer-elements tx-event-fifo-elements tx-buffer-elements>

The 'offset' is an address offset of the message RAM where the following elements start
from. This is normally set to 0x0 when using a non-shared message RAM. The remaining cells
specify how many elements are allocated for each filter type/FIFO/buffer.

The Bosch M_CAN IP supports the following elements:
11-bit Filter	 0-128 elements / 0-128 words
29-bit Filter	  0-64 elements / 0-128 words
Rx FIFO 0		    0-64 elements / 0-1152 words
Rx FIFO 1		    0-64 elements / 0-1152 words
Rx Buffers	    0-64 elements / 0-1152 words
Tx Event FIFO	  0-32 elements / 0-64 words
Tx Buffers	    0-32 elements / 0-576 words

Configures the internal timestamp counter time unit in multiples of CAN bit times. Valid range
is 1 to 16. The default value is a prescaler of 1, such that the time unit equals one CAN bit
time.

Deprecated. This property has been renamed to bitrate-data.

Initial data phase bitrate in bit/s.  If this is unset, the initial data phase bitrate is set
to CONFIG_CAN_DEFAULT_BITRATE_DATA.

Initial data phase sample point in per mille (e.g. 875 equals 87.5%).

If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for
bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other
bitrates.

Deprecated. This property has been renamed to bitrate.

Initial bitrate in bit/s. If this is unset, the initial bitrate is set to
CONFIG_CAN_DEFAULT_BITRATE.

Initial sample point in per mille (e.g. 875 equals 87.5%).

bitrates.

Actively controlled CAN transceiver.

Example:
  transceiver0: can-phy0 {
    compatible = "nxp,tja1040", "can-transceiver-gpio";
    standby-gpios = <gpioa 0 GPIO_ACTIVE_HIGH>;
    max-bitrate = <1000000>;
    #phy-cells = <0>;
  };

  &can0 {
    status = "okay";

    phys = <&transceiver0>;
  };

fdcan1: can@40006400 {
  compatible = "st,stm32-fdcan";
  reg = <0x40006400 0x400>, <0x4000b400 0x350>;
  reg-names = "m_can", "message_ram";
  interrupts = <21 0>, <22 0>;
  interrupt-names = "int0", "int1";
  clocks = <&rcc STM32_CLOCK(APB1, 12)>,
           <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
  bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
  status = okay";
};

Passive CAN transceiver. The child node must be named "can-transceiver".

Example:
  &can0 {

    can-transceiver {
      max-bitrate = <1000000>;
    };
  };

The minimum bitrate supported by the CAN transceiver in bits/s.

The maximum bitrate supported by the CAN transceiver in bits/s.

Clock divider at the input of the lptimer clock, default reset value is 'not divided'.

Prescaler allows to achieve higher LPTIM timeout (up to 256s when lptim clocked by LSE)
and consequently higher core sleep durations, but impacts the tick precision.
To be used with caution.
CONFIG_SYS_CLOCK_TICKS_PER_SEC could be used to tune tick duration and gain precision,
at kernel timing granularity cost.

For example, when LPTIM is clocked by the LSE (32768Hz) and st,prescaler = <32>:
LPTIM global timeout is 64 seconds with an increment of 0.97 ms.
Using CONFIG_SYS_CLOCK_TICKS_PER_SEC = 4096, tick = 0.24 ms, LPTIM precision is 4 ticks.
Using CONFIG_SYS_CLOCK_TICKS_PER_SEC = 1024, tick = 0.97 ms, LPTIM precision is 1 ticks.

Gives the LPTIM an exact counting value (s) for timeout expiration.
Valid range is [1, 256] and should be consistent with st,prescaler
pre-defined setting. If not, an error is raised.

Sets the dead-time configuration on the associated timer which will add
a delay between the rising edge of the reference signal and the rising
edge of both the OCx and OCxN signals. This is commonly used and required
with bridge circuits to prevent shoot-through currents.

This feature is supported only by certain timer instances. Refer
to your product's Reference Manual for more information about this
feature's availability. (In particular, certain series such as
STM32L0/STM32L1 have no instance supporting this feature).

Valid range [0 ... 255].

}

The lptim node to be used for counting ticks during lowpower modes
must be named stm32_lp_tick_source in the DTS.

Clock prescaler at the input of the timer
Could be in range [0 .. 0xFFFF] for STM32 General Purpose Timers (CLK/(prescaler+1) )

Sets timer counter mode.

Use constants defined in dt-bindings/timer/stm32-timer.h.

* STM32_TIM_COUNTERMODE_UP             - used as upcounter.
* STM32_TIM_COUNTERMODE_DOWN           - used as downcounter.
* STM32_TIM_COUNTERMODE_CENTER_DOWN    - counts up and down alternatively.
                                         Output compare interrupt flags of output channels
                                         are set only when the counter is counting down.
* STM32_TIM_COUNTERMODE_CENTER_UP      - counts up and down alternatively.
                                         are set only when the counter is counting up.
* STM32_TIM_COUNTERMODE_CENTER_UP_DOWN - counts up and down alternatively.
                                         are set only when the counter is counting up or
                                         down.

If absent, then STM32_TIM_COUNTERMODE_UP is used (reset state).

Selects master mode (trigger output TRGO source selection)
of the timer instance. Only available for timer instances
with master function - property is ignored otherwise.

For details, refer to your device's Reference Manual.

* RESET   - The UG bit from the TIMx_EGR register is used
            as TRGO.
* ENABLE  - The Counter enable signal, CNT_EN, is used as TRGO.
* UPDATE  - The update event is used as TRGO.
* CC1IF   - The CC1IF set event is used as TRGO.
* OC1REF - OC1REF signal is used as TRGO.
* OC2REF - OC2REF signal is used as TRGO.
* OC3REF - OC3REF signal is used as TRGO.
* OC4REF - OC4REF signal is used as TRGO.

Add support to capture on four channels. This is less accurate than
the default 2 channel support because the counter is reset by
interrupt instead of slave-mode controller. This option can also
be used as alternative for timers that does not support slave mode.

Number of items to expect in a PWM
- channel of the timer used for PWM
- period to set in ns
- flags : combination of standard flags like PWM_POLARITY_NORMAL
  or specific flags like STM32_PWM_COMPLEMENTARY. As an example,
  the following complementary PWMs(CH2&CH2N) are shown below.
    <&pwm1 2 100 (PWM_POLARITY_NORMAL)>;
    <&pwm1 2 100 (PWM_POLARITY_NORMAL | STM32_PWM_COMPLEMENTARY)>;

Set encoder mode.
The following modes are supported:
0x1: Encoder mode 1 (Default)
0x2: Encoder mode 2
0x3: Encoder mode 3
Some MCUs supports additional modes:
0x10002: Encoder mode: Clock plus direction, x2 mode
0x10003: Encoder mode: Clock plus direction, x1 mode
0x10004: Encoder mode: Directional Clock, x2 mode
0x10005: Encoder mode: Directional Clock, x1 mode
0x10006: Quadrature encoder mode: x1 mode, counting on tim_ti1fp1
0x10007: Quadrature encoder mode: x1 mode, counting on tim_ti2fp2
Default value complies with stm32 low level timer encoder init value.

Intensity of the filter applied to the input signal. This is
implemented by scaling the sampling frequency and adding a counter
in which N consecutive samples with same value are needed to validate
a transition.
Mapping is as follows (F_clk is the timer's clock):
0: No filter, sampling is done at F_dts (default value)
1: Fs = F_clk, N=2
2: Fs = F_clk, N=4
3: Fs = F_clk, N=8
4: Fs = F_clk/2, N=6
5: Fs = F_clk/2, N=8
6: Fs = F_clk/4, N=6
7: Fs = F_clk/4, N=8
8: Fs = F_clk/8, N=6
9: Fs = F_clk/8, N=8
10: Fs = F_clk/16, N=5
11: Fs = F_clk/16, N=6
12: Fs = F_clk/16, N=8
13: Fs = F_clk/32, N=5
14: Fs = F_clk/32, N=6
15: Fs = F_clk/32, N=8
Default value is set by hardware at reset

This is a number >= 1 that is used to determine how many revolutions
were done based on the current counter's value.

Human readable string describing the sensor. It can be used to
distinguish multiple instances of the same model (e.g., lid accelerometer
vs. base accelerometer in a laptop) to a host operating system.

This property is defined in the Generic Sensor Property Usages of the HID
Usage Tables specification
(https://usb.org/sites/default/files/hut1_3_0.pdf, section 22.5).

RTC synchronous prescaler value. Optional, if not set defaulted in code to:
- Selected to give 1 Hz tick rate, based on source clock frequency and asynchronous
  prescaler value.

RTC asynchronous prescaler value. Optional, if not set defaulted in code to:
- 0x7F if RTC source clock is LSE/LSI
- 1 if using counter with CONFIG_COUNTER_RTC_STM32_SUBSECONDS option
- 0x7C if RTC source clock is HSE

RTC HSE prescaler value. Applies only when RTC source clock is HSE.
Optional, defaulting to the value calculated based on HSE clock frequency
to give the highest possibly prescaled source frequency below 1MHz.

Number of alarms supported by STM32 RTC device.
Most of STM32 MCU series have 2 RTC alarms, A & B.
Defaults to 0 when not declared in devicetree.

Number of the Extended Interrupts and Event Controller (EXTI) interrupt
line connected to the RTC Alarm event.
Not required, since RTC Alarm interrupt could be routed directly to Nested
Vectored Interrupt Controller (NVIC) and to Power Control (PWR) wake-up
pins on some series.

RTC frequency equals clock-frequency divided by the prescaler value

Specifies the clock line to be enabled in clock controller as well as
the clock domain used, for instance:
          <&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */
A correctly configured domain clock is required to allow the integrated low
sampling clock detection mechanism to behave properly.
In the provided example, MSI should be configured to provide 48Mhz clock.

This property is used to configure the RNG_CR for the NIST certification
The validation conditions are following the refMan
to certify NIST SP800-90B. RNG clock source must be 48MHz.
This config is valid with some STM32 families
and when Conditioning Soft Reset (RNG_CR_CONDRST bit) exists.
The value is directly mapped from the RNG configuration (A) table.
The Health Register (health-test-config property) must correspond
to this table configuration.
On the stm32U5, the ARDIS bit7 is also written.

Magic Number to be written to Health Test Configuration Register (HTCR)
prior to real configuration, if any.

Heath Test Configuration, necessary to have proper RNG behavior,
when available.

This property is used to configure the RNG_NSCR register for the NIST
certification.

Size of USB dedicated RAM. STM32 SOC's reference
manual defines USB packet SRAM size.

Some boards use a USB DISCONNECT pin to enable
the pull-up resistor on USB Data Positive signal.

Number of bi-directional endpoints supported by hardware
(including EP0)

Number of IN endpoints supported by hardware
(including EP0 IN)

Number of OUT endpoints supported by hardware
(including EP0 OUT)

Configures USB controllers to work up to a specific speed. Valid arguments are "super-speed", "high-speed", "full-speed" and "low-speed". If this is not passed via DT, USB controllers should use their maximum hardware capability.

This binding is to be used by all the usb transceivers which are built-in
with USB IP

Number of cells in a PHY provider. The meaning those
cells is defined by the binding for the phy node.

STM32 DMA controller (V2)

It is present on stm32 devices like stm32L4 or stm32WB.
This DMA controller includes several channels with different requests.
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a four-cell specifier for each
capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
described in the dma.txt file, using a 3-cell specifier for each
channel: a phandle to the DMA controller plus the following four integer cells:
  1. channel: the dma stream from 1 to <dma-requests>
  2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
  this value is 0 for Memory-to-memory transfers
  or a value between <1> .. <dma-generators> (not supported yet)
  or a value between <dma-generators>+1  ..  <dma-generators>+<dma-requests>
  3. channel-config: A 32bit mask specifying the DMA channel configuration
  A name custom DMA flags for channel configuration is used
  which is device dependent. See stm32_dma.h:
    -bit 5 : DMA  cyclic mode config
              0x0: STM32_DMA_MODE_NORMAL
              0x1: STM32_DMA_MODE_CYCLIC
    -bit 6-7 : Direction (see dma.h)
              0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
              0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
              0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
              0x3: reserved for PERIPH to PERIPH
    -bit 9 : Peripheral Increment Address
             0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
             0x1: STM32_DMA_PERIPH_INC: increment address between transfers
    -bit 10 : Memory Increment Address
             0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
             0x1: STM32_DMA_MEM_INC: increment address between transfers
    -bit 11-12 : Peripheral data size
             0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
             0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
             0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
             0x3: reserved
    -bit 13-14 : Memory data size
             0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
             0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
             0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
    -bit 15: Reserved
    -bit 16-17 : Priority level
             0x0: STM32_DMA_PRIORITY_LOW: low
             0x1: STM32_DMA_PRIORITY_MEDIUM: medium
             0x2: STM32_DMA_PRIORITY_HIGH: high
             0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high

Example of dma usual combination for peripheral transfer
     #define STM32_DMA_PERIPH_TX	(STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
     #define STM32_DMA_PERIPH_RX	(STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)

Example of dma node for stm32wb55x
   dma2: dma-controller@40020400 {
       compatible = "st,stm32-dma-v2";
       ...
       dma-requests = <7>;
       status = "disabled";
      };

For the client part, example for stm32l476 on DMA1 instance
  Tx using channel 3 with request 1
  Rx using channel 2 with request 1
  spi1 {
   compatible = "st,stm32-spi";
   dmas = <&dma1 3 1 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
          <&dma1 2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
   dma-names = "tx", "rx";
  };

offset in the table of channels when mapping to a DMAMUX
for 1st dma instance, offset is 0,
for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
plus the nb of dma channels of the 1st dma instance, etc.

Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.

Memory address alignment requirement for DMA buffers used by the controller.

Memory size alignment requirement for DMA buffers used by the controller.

STM32 DMAMUX controller

The STM32 DMAMUX is a direct memory access multiplexer
capable of supporting independent DMA channels.
DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
  1. channel: the mux channel from 0 to <dma-channels> - 1
  2. slot: the request line Multiplexer ID
  which is device dependent:
      -bit 6-7 : Direction  (see dma.h)
             0x0: MEM to MEM
             0x1: MEM to PERIPH
             0x2: PERIPH to MEM
             0x3: reserved for PERIPH to PERIPH
      -bit 9 : Peripheral Increment Address
             0x0: no address increment between transfers
             0x1: increment address between transfers
      -bit 10 : Memory Increment Address
      -bit 11-12 : Peripheral data size
             0x0: Byte (8 bits)
             0x1: Half-word (16 bits)
             0x2: Word (32 bits)
      -bit 13-14 : Memory data size
      -bit 15: Peripheral Increment Offset Size not USED for DMA V2
             0x0: offset size is linked to the peripheral bus width
             0x1: offset size is fixed to 4 (32-bit alignment)
      -bit 16-17 : Priority level
             0x0: low
             0x1: medium
             0x2: high
             0x3: very high
 example for stm32wb55x
   dmamux1: dmamux@40020800 {
       compatible = "st,stm32-dmamux";
       ...
       dma-channels = <14>;
       dma-generators = <4>;
       dma-requests= <36>;
      };
  for client SPI of stm32wb55x
   spi1: spi@40013000 {
       compatible = "st,stm32-spi";
       dmas = <&dmamux1 11 7 0x20440
                &dmamux1 1 6 0x20480>;
       dma-names = "tx", "rx";
      };

Number of DMAMUX output request channels supported by the controller

Number of DMAMUX Peripheral Request Line inputs supported by the controller
This is not directly the value to program in the DMAREQ_ID of the DMAMUX_CxCR

STM32 USB Type-C / Power Delivery.

The default values were taken from the LL_UCPD_StructInit function defined in the HAL.

Determines the division ratio of a kernel clock pre-scaler
producing UCPD peripheral clock (ucpd_clk). It is recommended
to use the pre-scaler so as to set the ucpd_clk frequency in
the range from 6 to 9 MHz.

Determines the division ratio of a ucpd_clk divider producing
inter-frame gap timer clock (tInterFrameGap).
The division ratio 15 is to apply for Tx clock at the USB PD 2.0
specification nominal value.
Valid range: 2 - 32

Determines the division ratio of a hbit_clk divider producing
tTransitionWindow interval.

half-bit clock (hbit_clk)
Valid range: 1 - 64

Determine if USB-C Dead Battery pull-down's should be
applied to the CC lines.

DMA channel name: "tx" or "rx", depending of expected device behavior.

Master Clock Output function.
An mck pin must be listed within pinctrl-0 when enabling this property.

Master Clock Divider Configuration.

When no-div property is present:
- MCKDIV = SAI_CK_x / (FS * (FRL + 1))
Otherwise:
- MCKDIV = SAI_CK_x / (FS * (OSR + 1) * 256)

When div-256 is present OSR is set to 0.
When div-512 is present OSR is set to 1.

Synchronous mode.
When present, the SAI controller is configured to work in synchronous mode.

SAI Block Fifo Threshold defines the fill level at which the peripheral
triggers a DMA request or interrupt to transfer data

One OPAMP has two inputs and one output. The three I/Os can be connected
to the external pins, enabling any type of external interconnection.
An OPAMP can be configured internally:
  - standalone amplifier (external gain setting mode)
  - follower
  - non-inverting amplifier with gains ranging from 2 to 64
  - inverting amplifier with gains ranging from -1 to -63

The positive input (INP) can be connected to the internal DAC.
The output (VOUT) can be connected to the internal ADC.

Main features:
  - Rail-to-rail input voltage range
  - Low input bias current
  - Low input offset voltage
  - High frequency gain bandwidth
  - High-speed mode to achieve a better slew rate
  - Self calibration support for better offset voltage adjustment
    of the input NMOS and PMOS transistors

Minimal DTS examples for OPAMP2:

  - Standalone amplifier (external gain):
    ```
    &opamp2 {
      pinctrl-0 = <&opamp2_vinm_pa5 &opamp2_vinp_pa7 &opamp2_vout_pa6>;
      pinctrl-names = "default";
      functional-mode = "standalone";
      inp = "VINP0";
      status = "okay";
    };
    ```
    NOTES: Following points regarding standalone mode are to be considered:
      - inm is tied to VINM0 independently of the value provided in DTS

  - Follower (voltage buffer):
    ```
    &opamp2 {
      pinctrl-0 = <&opamp2_vout_pa6>;
      functional-mode = "follower";
      inp = "DAC";
    };
    ```

  - Non-inverting PGA (gain 2..64):
    ```
    &opamp2 {
      pinctrl-0 = <&opamp2_vinp_pb14 &opamp2_vout_pa6>;
      functional-mode = "non_inverting";
      inp = "VINP1";
    };
    ```

  - Inverting PGA (gain -1..-63):
    ```
    &opamp2 {
      pinctrl-0 = <&opamp2_vinm_pc5 &opamp2_vinp_pb0
                   &opamp2_vout_pa6>;
      functional-mode = "inverting";
      inp = "VINP2"; /* shall be routed to external bias voltage */
      inm = "VINM0"; /* VINM0 is only allowed choice */
    };
    ```

Timer-controlled input MUX (non-inverting PGA):
  - Switch between VINP0 and VINP3 on TIM1_CH6 trigger.
  ```
  &opamp2 {
    pinctrl-0 = <&opamp2_vinm_pa5 &opamp2_vinm_pc5
                 &opamp2_vinp_pa7 &opamp2_vout_pa6>;
    pinctrl-names = "default";
    functional-mode = "standalone";
    st,inputs-mux-mode = "TIM1_CH6";
    inp = "VINP0", "VINP3";
  };
  ```

Usage with an ADC:
  ```
  / {
      zephyr,user {
        opamp = <&opamp2>;
      };
    };

    &adc2 {
      st,adc-clock-source = "SYNC";
      st,adc-prescaler = <4>;

      #address-cells = <1>;
      #size-cells = <0>;

      channel@3 {
        reg = <3>;
        zephyr,gain = "ADC_GAIN_1";
        zephyr,reference = "ADC_REF_INTERNAL";
        zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
        zephyr,resolution = <12>;
        zephyr,vref-mv = <3300>;
      };
    };

    &opamp2 {
      pinctrl-0 = <&opamp2_vinm_pa5 &opamp2_vinp_pa7>;
      inm = "VINM0";
      io-channels = <&adc2 3>;
    };
    ```
  NOTE: ADC can be read from the code with usual ADC API.

NOTE: It is highly recommended to take a look at RM0440 Rev 9 and AN5306
      for more details about STM32G4 OPAMP features and usage.

References:
  - AN5306:
    https://www.st.com/resource/en/application_note/an5306-operational-amplifier-opamp-usage-in-stm32g4-series-stmicroelectronics.pdf
  - RM0440 Rev 9:
    https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/7c/b0/25/29/1b/a2/42/b2/DM00355726/files/DM00355726.pdf/jcr:content/translations/en.DM00355726.pdf

OPAMP power mode has impact on slew-rate:
  - NORMAL - slew-rate 6.5 V/µs with low power consumption.
  - HIGHSPEED - slew-rate 45 V/µs with higher power consumption.
source: https://www.st.com/resource/en/product_training/STM32G4-Analog-OPAMP_OPAMP.pdf

Lock the OPAMP configuration after it has been configured by the driver.
Resetting the lock mode can only be done by a system reset.
If not set, the OPAMP configuration will be unlocked by default.
The lock property is used to prevent accidental changes to the OPAMP
configuration after it has been set.
NOTES:
  - In st,inputs-mux-mode the timer mux register will be locked too

Enable self-calibration mode.
If not set, the self-calibration mode will be disabled by default.
The self-calibration mode is used to calibrate the OPAMP for optimal
performance.
NOTES:
  - This step will be executed at OPAMP initialization

Non-Inverting input selection.
Please refer to RM0440 Rev 9, Table 204. pp. 777/2140 for more details.
NOTES:
  - Selecting st,inputs-mux-mode expects secondary input entry too

Inverting input selection.
NOTES:
  - In case st,inputs-mux-mode is selected:
    * In standalone mode muxed between VINM0 and VINM1 (VM_SEL = '00' or '01')
    * In inverting/non_inverting (VM_SEL = '10') or follower (VM_SEL = '11') mode
      muxed between resistor feedback and VOUT.
      Basically, multiplexing happens between PGA and follower modes.
      ATTENTION: No VINM0/VINM1 multiplexing happens here!
  - The values in the array shall be ordered (e.g. VINM0, VINM1)

Inverting input filtering selection.
Please refer to RM0440 Rev 9 pp. 783-784/2140 for more details.
NOTES:
  - Only applicable in inverting/non_inverting PGA modes

Timer controlled multiplexer mode.
The selection of the OPAMP inverting and non inverting inputs can be done automatically. In
this case, the switch from one input to another is done automatically. This automatic switch
is triggered by the TIM1 CC6 or TIM8 CC6 or TIM20 CC6 output arriving on the OPAMP
input multiplexers.
This is useful for dual motor control with a need to measure the currents on the 3 phases
simultaneously on a first motor and then on the second motor.
Please refer to RM0440 Rev 9, 25.3.8 Timer controlled Multiplexer mode, pp. 786/2140

OPAMP PMOS transistor offset trimming value.
The value will be applied directly to TRIMOFFSETP[4:0] (Bits 23:19 in OPAMPx_CST register).
If value is present and self-calibration is enabled, this value will overwrite values
calculated during self-calibration.
Please refer to RM0440 Rev 9, pp. 789/2140 for more details.
NOTE: Acceptable range is 0x00 to 0x1f.

OPAMP NMOS transistor offset trimming value.
The value will be applied directly to TRIMOFFSETN[4:0] (Bits 28:24 in OPAMPx_CST register).

Selects opamp functional mode.

a) differential mode

- Signals applied to both inputs
- Amplifies the difference between two input signals
- Common-mode signals are rejected
- Used in instrumentation and noise rejection
- Vout = (Rf/Rin) * (Vin2 - Vin1), where Rf is the feedback resistor
  and Rin is the input resistor, with gain (Rf/Rin)

         Rin        Rf
Vin1 --/\/\/\--*--/\/\/\-----
               |            |
               |     |\     |
               ------|- \   |
                     |   >--*-- Vout
               ------|+ /
               |     |/
               |
Vin2 --/\/\/\--*--/\/\/\-----
         Rin        Rf      |
                           GND

b) inverting mode

- Input signal applied to inverting (-) terminal
- Non-inverting (+) terminal connected to ground
- Feedback resistor connects output to inverting input
- Output is 180° out of phase with input
- Vout = (-Rf/Rin) * Vin, where Rf is the feedback resistor
  and Rin is the input resistor, s.t. gain is (-Rf/Rin)

        Rin        Rf
Vin --/\/\/\--*--/\/\/\-----
              |            |
              |     |\     |
              ------|- \   |
                    |   >--*-- Vout
              ------|+ /
              |     |/
            GND

c) non_inverting mode

- Input signal applied to non-inverting (+) terminal
- Inverting (-) terminal connected to feedback network
- Output is in phase with input
- Vout = (1 + (Rf/Rin)) * Vin, where Rf is the feedback resistor
  and Rin is the input resistor, s.t. gain is (1 + (Rf/Rin))

      Rin        Rf
 |--/\/\/\--*--/\/\/\-----
 |          |            |
GND         |     |\     |
            ------|- \   |
                  |   >--*-- Vout
        Vin ------|+ /
                  |/

d) follower mode (voltage follower or buffer)

- Special case of non-inverting amplifier
- Vout = 1 * Vin, s.t. gain is 1
- Direct feedback from output to inverting input
- Very high input impedance, very low output impedance
- Used for impedance matching

    --------------
    |            |
    |     |\     |
    ------|- \   |
          |   >--*-- Vout
Vin ------|+ /
          |/

e) standalone mode

- The opamp mode is defined by external circuitry

          |\
Vin- -----|- \
          |   >---- Vout
Vin+ -----|+ /
          |/

  - https://www.electronics-tutorials.ws/category/opamp

If the OPAMP supports programmable gain, then the gain of
the opamp can be changed dynamically at runtime. The gain
value needs to be one of the enumerations above.
- OPAMP_GAIN_1_7  : x 1/7
- OPAMP_GAIN_1_3  : x 1/3
- OPAMP_GAIN_1    : x 1
- OPAMP_GAIN_5_3  : x 5/3
- OPAMP_GAIN_2    : x 2
- OPAMP_GAIN_11_5 : x 11/5
- OPAMP_GAIN_3    : x 3
- OPAMP_GAIN_4    : x 4
- OPAMP_GAIN_13_3 : x 13/3
- OPAMP_GAIN_7    : x 7
- OPAMP_GAIN_8    : x 8
- OPAMP_GAIN_15   : x 15
- OPAMP_GAIN_16   : x 16
- OPAMP_GAIN_31   : x 31
- OPAMP_GAIN_32   : x 32
- OPAMP_GAIN_33   : x 33
- OPAMP_GAIN_63   : x 63
- OPAMP_GAIN_64   : x 64

Disables an undocumented compare feature (sets COMP_CxCSR bit #1 to 0) which
holds the comparator output during the duration of the Miller effect.
NOTE: This setting is supported only by stm32g4x series.
NOTE: It is recommended to enable the feature unless very fast events are tracked.
Please refer to following url for details:
https://community.st.com/t5/stm32-mcus-products/stm32g431-comparator-bug/m-p/679540#M250779

EXTI interrupt line number connected to the comparator (COMPx) event.

The comparator configuration can be locked to prevent any
modification until the next system reset.
Once the lock bit is set, it can be cleared only by a system reset.
This feature allows to protect the comparator configuration against
unintentional modification.

Cyclic Redundancy Check (CRC) calculation unit with
programmable initial value and programmable polynomials
of 7-, 8-, 16- and 32-bit size.

Minimum residency duration in microseconds.

How much time the residency in a given idle state must last for state entry
to be worthwhile energywise. It includes the time to enter into this state
and represents the "break-even" time to justify the time and power spent
on the work needed for entering and exiting the state based on how much actual energy
is saved once in the state, compared to choosing the next shallowest state.

Worst case latency in microseconds required to exit the idle state.

Disable system managed device power management for this state. When set,
the power management subsystem will not suspend devices before entering
this state.

Signify that this node should result in a dedicated linker script
memory region in the final executable. The region address and size
is taken from the <reg> property, while the name is the value of
this property.

Set attributes such as read-only or executable for the linker script
memory region. The string set here will be specified in parentheses
after the area name in the linker script.

Signify that this node should result in a dedicated MPU region.
Deprecated in favor of 'zephyr,memory-attr'.

Attribute or set of attributes (bitmask) for the memory region. See
'include/zephyr/dt-bindings/memory-attr/memory-attr.h' for a
comprehensive list with description of possible values.

LSE driving capability, within the range 0 to 3.
0 represents the lowests driving capability, 3
the highest.

LSE crystal oscillator bypass
Set the property to by-pass the oscillator with an external clock.

STM32 family TEMP node for production calibrated sensors with two calibration temperatures.

Two NVMEM cells must be provided:
  - TS_CAL1
  - TS_CAL2

Each cell corresponds to the eponymous calibration parameter.

NVMEM cell(s) containing sensor calibration parameter(s).

Refer to description of `nvmem-cell-names` for details.

Analog voltage reference (Vref+) voltage with which
temperature sensor calibration parameters have been
measured

ADC resolution used for measuring calibration data

This is usually equal to the ADC's native resolution.

Most series have a 12-bit ADC, but 14-bit and 16-bit
also exists on e.g., STM32U5 and STM32H7 (16) series.

One entry corresponding to the VREFINT_CAL calibration parameter
(factory-measured calibration bandgap voltage) must be provided.

VDDA/VREF+ voltage in millivolts applied during manufacturing to determine
the internal bandgap voltage reference VREFINT.

also exists on e.g., STM32U5 and STM32H7 series.

GPIO pins exposed on Arduino Uno (R3) headers.

The Arduino Uno layout provides four headers, two each along
opposite edges of the board.

Proceeding counter-clockwise:
* An 8-pin Power Supply header.  No pins on this header are exposed
  by this binding.
* A 6-pin Analog Input header.  This has analog input signals
  labeled from A0 at the top through A5 at the bottom.
* An 8-pin header (opposite Analog Input).  This has digital input
  signals labeled from D0 at the bottom D7 at the top;
* A 10-pin header (opposite Power Supply).  This has six additional
  digital input signals labelled from D8 at the bottom through D13
  towards the top, skipping two pins, then finishing with D14 and
  D15 at the top.

This binding provides a nexus mapping for 20 pins where parent pins 0
through 5 correspond to A0 through A5, and parent pins 6 through 21
correspond to D0 through D15, as depicted below:

                             D15  21
                             D14  20
                             AREF -
                             GND  -
    - N/C                    D13  19
    - IOREF                  D12  18
    - RESET                  D11  17
    - 3V3                    D10  16
    - 5V                     D9   15
    - GND                    D8   14
    - GND
    - VIN                    D7   13
                             D6   12
    0 A0                     D5   11
    1 A1                     D4   10
    2 A2                     D3    9
    3 A3                     D2    8
    4 A4                     D1    7
    5 A5                     D0    6

Use ARDUINO_HEADER_R3_* constants in <zephyr/dt-bindings/gpio/arduino-header-r3.h> to refer to
specific pins using convenient constant names.

GPIO pins exposed on ST Morpho connector.

The ST morpho connector consists in male pin headers (CN7 and CN10 in case of
Nucleo-64, CN11 and CN12 in case of Nucleo-144) accessible on both sides of
any Nucleo board. They can be used to connect shields. All signals and power
pins of the STM32 are available on the ST morpho connector.

Use ST_MORPHO_* constants in <zephyr/dt-bindings/gpio/st-morpho-header.h>
to refer to specific pins using convenient constant names.

Group of GPIO-controlled LEDs.

Each LED is defined in a child node of the gpio-leds node.

Human readable string describing the LED. It can be used by an
application to identify this LED or to retrieve its number/index
(i.e. child node number) on the parent device.

/ {
  leds {
    compatible = "gpio-leds";
    /*
     * led_0 is pin 1 on gpio0.
     * The LED is on when the pin is low, and off when the pin is high.
     */
    led_0 {
      gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
    };
    /*
     * led_1 is pin 2 on gpio0.
     * The LED is on when the pin is high, and off when it is low.
     */
    led_1 {
      gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
    };
    /*
     * led_2 is pin 15 on gpio1.
     * The LED is on when the pin is low, and the pin's internal pull-up resistor should be
     * enabled.
     */
    led_2 {
      gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
    };
  };
};

Group of PWM-controlled LEDs.

Each LED is defined in a child node of the pwm-leds node.

Reference to a PWM instance.

The period field is used by the set_brightness function of the LED API.
Its value should at least be greater that 100 nanoseconds (for a full
brigtness granularity) and lesser than 50 milliseconds (average visual
persistence time of the human eye). Typical values for the PWM period
are 10 or 20 milliseconds.

Group of GPIO-bound input keys.

This defines a group of buttons that can generate input events. Each button
is defined in a child node of the gpio-keys node and defines a specific key
code.

Debouncing interval time in milliseconds.
If not specified defaults to 30.

Do not use interrupts for the key GPIOs, poll the pin periodically at the
specified debounce-interval-ms instead.

Action taken by driver on key GPIOs when device is suspended.

none:
  No action - GPIO pins are not reconfigured.
  Useful when the GPIO controller does not support GPIO_DISCONNECTED.

disconnect-with-pupd:
  This option is provided mainly for backwards compatibility.
  You probably want to use `full-disconnect` instead.

  GPIO pins are reconfigured in GPIO_DISCONNECTED state using a call
  to gpio_pin_configure_dt() which is identical to `full-disconnect`
  if Devicetree does not contain flag GPIO_PULL_DOWN or GPIO_PULL_UP.
  Otherwise, the behavior is implementation-defined:
  - the requested pull-down/pull-up resistor may or may not be enabled
  - the GPIO controller driver may reject the request (-ENOTSUP)

full-disconnect:
  Fully disconnect GPIO pins (reconfigure without PU/PD flags)

  to gpio_pin_configure() with all flags from Devicetree unchanged,
  except GPIO_PULL_DOWN and GPIO_PULL_UP which are masked out.

  This should place GPIO pins in an high-impedance/"floating" state.

The default value is `disconnect-with-pupd` for backwards compatibility.

#include <zephyr/dt-bindings/input/input-event-codes.h>

/ {
       buttons {
               compatible = "gpio-keys";
               button_0 {
                       gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
                       zephyr,code = <INPUT_KEY_0>;
               };
       };
};

QEMU, a generic and open source machine emulator and virtualizer

Antmicro's open source simulation and virtual development framework

Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.)

Virtual I/O Device Specification, developed by the OASIS consortium

A stand-in for a real vendor which can be used in examples and tests

STM32 Comparator

The following example displays the minimum node layout:

    reg = <0x40010200 0x4>;
    interrupts = <64 0>;
    clocks = <&rcc STM32_CLOCK(APB2, 0)>;
    st,exti-line = <21>;
    positive-input = "IN0";
    negative-input = "VREFINT";
  };

NOTE: The shown example is for stm32g474re

Enabling the comparator node requires setting the minimum default
configuration of the comparator. This includes selecting the
positive and negative inputs, and routing them using pinctrl:

  &comp1 {
    pinctrl-0 = <&comp1_inp_pa1 &comp1_out_pa6>;

  };

NOTE: Pins used above are an example for stm32g474re

Selects positive input pin provided by the pinmux controller.
IN0 corresponds to the first pinmux option, IN1 to the second one.

Selects negative input. May be a package pin (IN0 / IN1) via pinctrl
or an internal signal (e.g. VREFINT, DAC).
In case of package pin assignment IN0 will correspond to first pinmux pin
option and IN1 to the second one.

Selects the hysteresis voltage level.
Hysteresis adds a voltage offset to the comparator threshold to prevent
unwanted output toggling when the input voltage is noisy or slowly
varying around the comparator threshold.

Blanking source to mask short spikes at PWM period start.
Ref (example): STM32G4 RM0440 Rev 8, 24.3.6.