/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   /home/jeremy/utat-dev/zephyrproject/build/mcuboot/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   $ZEPHYR_BASE/dts/bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /connector
 *   4   /soc
 *   5   /soc/interrupt-controller@e000e100
 *   6   /clocks
 *   7   /clocks/clk-hse
 *   8   /clocks/pll
 *   9   /soc/rcc@40021000
 *   10  /soc/adc@50000000
 *   11  /soc/flash-controller@40022000
 *   12  /soc/flash-controller@40022000/flash@1fff7500
 *   13  /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout
 *   14  /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal1@a8
 *   15  /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal2@ca
 *   16  /dietemp
 *   17  /memory@20000000
 *   18  /soc/pin-controller@48000000
 *   19  /soc/pin-controller@48000000/i2c1_scl_pb8
 *   20  /soc/pin-controller@48000000/i2c1_sda_pb9
 *   21  /soc/i2c@40005400
 *   22  /smbus1
 *   23  /soc/i2c@40005800
 *   24  /smbus2
 *   25  /soc/i2c@40007800
 *   26  /smbus3
 *   27  /st-morpho-header
 *   28  /vbat
 *   29  /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/vrefint@aa
 *   30  /vref
 *   31  /clocks/clk-hsi
 *   32  /clocks/clk-hsi48
 *   33  /clocks/clk-lse
 *   34  /clocks/clk-lsi
 *   35  /cpus
 *   36  /cpus/power-states
 *   37  /cpus/power-states/state0
 *   38  /cpus/power-states/state1
 *   39  /cpus/cpu@0
 *   40  /soc/pin-controller@48000000/gpio@48000800
 *   41  /gpio_keys
 *   42  /gpio_keys/button
 *   43  /soc/pin-controller@48000000/gpio@48000000
 *   44  /leds
 *   45  /leds/led_0
 *   46  /soc/rcc@40021000/reset-controller
 *   47  /soc/timers@40000000
 *   48  /soc/pin-controller@48000000/tim2_ch1_pa5
 *   49  /soc/timers@40000000/pwm
 *   50  /pwmleds
 *   51  /pwmleds/green_pwm_led
 *   52  /soc/adc@50000100
 *   53  /soc/can@40006400
 *   54  /soc/comparator@40010200
 *   55  /soc/comparator@40010204
 *   56  /soc/crc@40023000
 *   57  /soc/pin-controller@48000000/dac1_out1_pa4
 *   58  /soc/dac@50000800
 *   59  /soc/dac@50001000
 *   60  /soc/dma@40020400
 *   61  /soc/dmamux@40020800
 *   62  /soc/interrupt-controller@40010400
 *   63  /soc/opamp1@40010300
 *   64  /soc/opamp2@40010304
 *   65  /soc/opamp3@40010308
 *   66  /soc/rng@50060800
 *   67  /soc/rtc@40002800
 *   68  /soc/dma@40020000
 *   69  /soc/sai1@40015404
 *   70  /soc/sai1@40015424
 *   71  /soc/serial@40004400
 *   72  /soc/serial@40004800
 *   73  /soc/serial@40004c00
 *   74  /soc/pin-controller@48000000/lpuart1_rx_pa3
 *   75  /soc/pin-controller@48000000/lpuart1_tx_pa2
 *   76  /soc/serial@40008000
 *   77  /soc/pin-controller@48000000/usart1_rx_pc5
 *   78  /soc/pin-controller@48000000/usart1_tx_pc4
 *   79  /soc/serial@40013800
 *   80  /soc/pin-controller@48000000/spi2_miso_pb14
 *   81  /soc/pin-controller@48000000/spi2_mosi_pb15
 *   82  /soc/pin-controller@48000000/spi2_nss_pb12
 *   83  /soc/pin-controller@48000000/spi2_sck_pb13
 *   84  /soc/spi@40003800
 *   85  /soc/pin-controller@48000000/spi3_miso_pc11
 *   86  /soc/pin-controller@48000000/spi3_mosi_pc12
 *   87  /soc/pin-controller@48000000/spi3_nss_pa15
 *   88  /soc/pin-controller@48000000/spi3_sck_pc10
 *   89  /soc/spi@40003c00
 *   90  /soc/pin-controller@48000000/gpio@48000400
 *   91  /soc/pin-controller@48000000/spi1_miso_pa6
 *   92  /soc/pin-controller@48000000/spi1_mosi_pa7
 *   93  /soc/pin-controller@48000000/spi1_sck_pa5
 *   94  /soc/spi@40013000
 *   95  /soc/timer@e000e010
 *   96  /soc/timers@40007c00
 *   97  /soc/ucpd@4000a000
 *   98  /usbphy
 *   99  /soc/usb@40005c00
 *   100 /soc/watchdog@40002c00
 *   101 /soc/watchdog@40003000
 *   102 /soc/flash-controller@40022000/flash@1fff7000
 *   103 /soc/flash-controller@40022000/flash@8000000
 *   104 /soc/flash-controller@40022000/flash@8000000/partitions
 *   105 /soc/flash-controller@40022000/flash@8000000/partitions/partition@0
 *   106 /soc/flash-controller@40022000/flash@8000000/partitions/partition@8800
 *   107 /soc/flash-controller@40022000/flash@8000000/partitions/partition@14800
 *   108 /soc/flash-controller@40022000/flash@8000000/partitions/partition@1f000
 *   109 /soc/pin-controller@48000000/gpio@48000c00
 *   110 /soc/pin-controller@48000000/gpio@48001000
 *   111 /soc/pin-controller@48000000/gpio@48001400
 *   112 /soc/pin-controller@48000000/gpio@48001800
 *   113 /soc/timers@40000000/counter
 *   114 /soc/timers@40000000/qdec
 *   115 /soc/timers@40000400
 *   116 /soc/timers@40000400/counter
 *   117 /soc/timers@40000400/pwm
 *   118 /soc/timers@40000400/qdec
 *   119 /soc/timers@40000800
 *   120 /soc/timers@40000800/counter
 *   121 /soc/timers@40000800/pwm
 *   122 /soc/timers@40000800/qdec
 *   123 /soc/timers@40001000
 *   124 /soc/timers@40001000/counter
 *   125 /soc/timers@40001400
 *   126 /soc/timers@40001400/counter
 *   127 /soc/timers@40012c00
 *   128 /soc/timers@40012c00/counter
 *   129 /soc/timers@40012c00/pwm
 *   130 /soc/timers@40012c00/qdec
 *   131 /soc/timers@40013400
 *   132 /soc/timers@40013400/counter
 *   133 /soc/timers@40013400/pwm
 *   134 /soc/timers@40013400/qdec
 *   135 /soc/timers@40014000
 *   136 /soc/timers@40014000/counter
 *   137 /soc/timers@40014000/pwm
 *   138 /soc/timers@40014400
 *   139 /soc/timers@40014400/counter
 *   140 /soc/timers@40014400/pwm
 *   141 /soc/timers@40014800
 *   142 /soc/timers@40014800/counter
 *   143 /soc/timers@40014800/pwm
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"
#define DT_N_FULL_NAME_UNQUOTED /
#define DT_N_FULL_NAME_TOKEN _
#define DT_N_FULL_NAME_UPPER_TOKEN _

/* Helpers for dealing with node labels: */
#define DT_N_NODELABEL_NUM 0
#define DT_N_FOREACH_NODELABEL(fn) 
#define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_FOREACH_ANCESTOR(fn) 

/* Helper macros for child nodes of this node. */
#define DT_N_CHILD_NUM 18
#define DT_N_CHILD_NUM_STATUS_OKAY 12
#define DT_N_CHILD_UNIT_ADDR_INT_536870912 DT_N_S_memory_20000000
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_dietemp) fn(DT_N_S_vref) fn(DT_N_S_vbat) fn(DT_N_S_usbphy) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_connector) fn(DT_N_S_st_morpho_header) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_usbphy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_st_morpho_header) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_usbphy, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_st_morpho_header, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_usbphy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_st_morpho_header, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_usbphy) fn(DT_N_S_connector) fn(DT_N_S_st_morpho_header) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_usbphy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_st_morpho_header) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_usbphy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_st_morpho_header, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_usbphy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_st_morpho_header, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__)

/* Node's hash: */
#define DT_N_HASH il7asoJjJEMhngUeSt4tHVu8Zxx4EFG_FDeJfL3_oPE

/* Node's dependency ordinal: */
#define DT_N_ORD 0
#define DT_N_ORD_STR_SORTABLE 00000

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /connector */ \
	4, /* /soc */ \
	6, /* /clocks */ \
	16, /* /dietemp */ \
	17, /* /memory@20000000 */ \
	22, /* /smbus1 */ \
	24, /* /smbus2 */ \
	26, /* /smbus3 */ \
	27, /* /st-morpho-header */ \
	28, /* /vbat */ \
	30, /* /vref */ \
	35, /* /cpus */ \
	41, /* /gpio_keys */ \
	44, /* /leds */ \
	50, /* /pwmleds */ \
	98, /* /usbphy */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_st_stm32g431rb_nucleo DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_FOREACH_REG(fn) 
#define DT_N_FOREACH_REG_SEP(fn, sep) 
#define DT_N_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_IRQ_LEVEL 0
#define DT_N_COMPAT_MATCHES_st_stm32g431rb_nucleo 1
#define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_COMPAT_MODEL_IDX_0 "stm32g431rb-nucleo"
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"st,stm32g431rb-nucleo"}
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_IDX_0 "st,stm32g431rb-nucleo"
#define DT_N_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g431rb-nucleo
#define DT_N_P_compatible_IDX_0_STRING_TOKEN st_stm32g431rb_nucleo
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G431RB_NUCLEO
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"
#define DT_N_S_aliases_FULL_NAME_UNQUOTED aliases
#define DT_N_S_aliases_FULL_NAME_TOKEN aliases
#define DT_N_S_aliases_FULL_NAME_UPPER_TOKEN ALIASES

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_aliases_NODELABEL_NUM 0
#define DT_N_S_aliases_FOREACH_NODELABEL(fn) 
#define DT_N_S_aliases_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_CHILD_NUM 0
#define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_aliases_HASH QavYY6yplHKhLPRKsRzaLCGlR0CWZ0JUNJakcBCfDXA

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1
#define DT_N_S_aliases_ORD_STR_SORTABLE 00001

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_FOREACH_REG(fn) 
#define DT_N_S_aliases_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_IRQ_LEVEL 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"
#define DT_N_S_chosen_FULL_NAME_UNQUOTED chosen
#define DT_N_S_chosen_FULL_NAME_TOKEN chosen
#define DT_N_S_chosen_FULL_NAME_UPPER_TOKEN CHOSEN

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_chosen_NODELABEL_NUM 0
#define DT_N_S_chosen_FOREACH_NODELABEL(fn) 
#define DT_N_S_chosen_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_CHILD_NUM 0
#define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_chosen_HASH qNExeeLInzqaWpm1KroyYDk4lRIxVO2ig78mq_hOnA8

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2
#define DT_N_S_chosen_ORD_STR_SORTABLE 00002

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_FOREACH_REG(fn) 
#define DT_N_S_chosen_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_IRQ_LEVEL 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /connector
 *
 * Node identifier: DT_N_S_connector
 *
 * Binding (compatible = arduino-header-r3):
 *   $ZEPHYR_BASE/dts/bindings/gpio/arduino-header-r3.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_connector_PATH "/connector"

/* Node's name with unit-address: */
#define DT_N_S_connector_FULL_NAME "connector"
#define DT_N_S_connector_FULL_NAME_UNQUOTED connector
#define DT_N_S_connector_FULL_NAME_TOKEN connector
#define DT_N_S_connector_FULL_NAME_UPPER_TOKEN CONNECTOR

/* Node parent (/) identifier: */
#define DT_N_S_connector_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_connector_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_connector_NODELABEL_NUM 1
#define DT_N_S_connector_FOREACH_NODELABEL(fn) fn(arduino_header)
#define DT_N_S_connector_FOREACH_NODELABEL_VARGS(fn, ...) fn(arduino_header, __VA_ARGS__)
#define DT_N_S_connector_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_connector_CHILD_NUM 0
#define DT_N_S_connector_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_connector_FOREACH_CHILD(fn) 
#define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_connector_HASH 1hNYiTso4N65bku_L_0pzRcHL_5NCz8DqiXd1i5KK7Q

/* Node's dependency ordinal: */
#define DT_N_S_connector_ORD 3
#define DT_N_S_connector_ORD_STR_SORTABLE 00003

/* Ordinals for what this node depends on directly: */
#define DT_N_S_connector_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_connector_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_connector_EXISTS 1
#define DT_N_INST_0_arduino_header_r3 DT_N_S_connector
#define DT_N_NODELABEL_arduino_header DT_N_S_connector

/* Macros for properties that are special in the specification: */
#define DT_N_S_connector_REG_NUM 0
#define DT_N_S_connector_FOREACH_REG(fn) 
#define DT_N_S_connector_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_RANGES_NUM 0
#define DT_N_S_connector_FOREACH_RANGE(fn) 
#define DT_N_S_connector_IRQ_NUM 0
#define DT_N_S_connector_IRQ_LEVEL 0
#define DT_N_S_connector_COMPAT_MATCHES_arduino_header_r3 1
#define DT_N_S_connector_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_connector_PINCTRL_NUM 0

/* Map properties: */
#define DT_N_S_connector_P_gpio_map_LEN 22
#define DT_N_S_connector_P_gpio_map_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0 10
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0 10
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_0 11
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_0 12
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_0 10
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_0 13
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_0 14
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_0 15
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_0 16
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_0 17
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_0 18
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_0 19
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_0 20
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_0 21
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY(fn) fn(DT_N_S_connector, gpio_map, 0) \
	fn(DT_N_S_connector, gpio_map, 1) \
	fn(DT_N_S_connector, gpio_map, 2) \
	fn(DT_N_S_connector, gpio_map, 3) \
	fn(DT_N_S_connector, gpio_map, 4) \
	fn(DT_N_S_connector, gpio_map, 5) \
	fn(DT_N_S_connector, gpio_map, 6) \
	fn(DT_N_S_connector, gpio_map, 7) \
	fn(DT_N_S_connector, gpio_map, 8) \
	fn(DT_N_S_connector, gpio_map, 9) \
	fn(DT_N_S_connector, gpio_map, 10) \
	fn(DT_N_S_connector, gpio_map, 11) \
	fn(DT_N_S_connector, gpio_map, 12) \
	fn(DT_N_S_connector, gpio_map, 13) \
	fn(DT_N_S_connector, gpio_map, 14) \
	fn(DT_N_S_connector, gpio_map, 15) \
	fn(DT_N_S_connector, gpio_map, 16) \
	fn(DT_N_S_connector, gpio_map, 17) \
	fn(DT_N_S_connector, gpio_map, 18) \
	fn(DT_N_S_connector, gpio_map, 19) \
	fn(DT_N_S_connector, gpio_map, 20) \
	fn(DT_N_S_connector, gpio_map, 21)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_SEP(fn, sep) fn(DT_N_S_connector, gpio_map, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 21)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 1, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 2, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 3, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 4, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 5, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 6, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 7, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 8, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 9, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 10, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 11, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 12, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 13, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 14, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 15, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 16, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 17, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 18, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 19, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 20, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 21, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 21, __VA_ARGS__)

/* Generic property macros: */
#define DT_N_S_connector_P_gpio_map_mask {4294967295 /* 0xffffffff */, 4294967232 /* 0xffffffc0 */}
#define DT_N_S_connector_P_gpio_map_mask_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_mask_IDX_0 4294967295
#define DT_N_S_connector_P_gpio_map_mask_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_mask_IDX_1 4294967232
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, gpio_map_mask, 0) \
	fn(DT_N_S_connector, gpio_map_mask, 1)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, gpio_map_mask, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_mask, 1)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map_mask, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map_mask, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_mask_LEN 2
#define DT_N_S_connector_P_gpio_map_mask_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru {0 /* 0x0 */, 63 /* 0x3f */}
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_0 0
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_1 63
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, gpio_map_pass_thru, 0) \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, gpio_map_pass_thru, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map_pass_thru, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map_pass_thru, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_pass_thru_LEN 2
#define DT_N_S_connector_P_gpio_map_pass_thru_EXISTS 1
#define DT_N_S_connector_P_compatible {"arduino-header-r3"}
#define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3"
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3
#define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_LEN 1
#define DT_N_S_connector_P_compatible_EXISTS 1
#define DT_N_S_connector_P_dma_coherent 0
#define DT_N_S_connector_P_dma_coherent_EXISTS 1
#define DT_N_S_connector_P_zephyr_deferred_init 0
#define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_connector_P_wakeup_source 0
#define DT_N_S_connector_P_wakeup_source_EXISTS 1
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"
#define DT_N_S_soc_FULL_NAME_UNQUOTED soc
#define DT_N_S_soc_FULL_NAME_TOKEN soc
#define DT_N_S_soc_FULL_NAME_UPPER_TOKEN SOC

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_NODELABEL_NUM 0
#define DT_N_S_soc_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_CHILD_NUM 50
#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 18
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_3758153984 DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_3758153744 DT_N_S_soc_S_timer_e000e010
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342177280 DT_N_S_soc_S_adc_50000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342177536 DT_N_S_soc_S_adc_50000100
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342179328 DT_N_S_soc_S_dac_50000800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342181376 DT_N_S_soc_S_dac_50001000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073881088 DT_N_S_soc_S_flash_controller_40022000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073876992 DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073808384 DT_N_S_soc_S_interrupt_controller_40010400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1207959552 DT_N_S_soc_S_pin_controller_48000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073821696 DT_N_S_soc_S_serial_40013800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073759232 DT_N_S_soc_S_serial_40004400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073760256 DT_N_S_soc_S_serial_40004800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073761280 DT_N_S_soc_S_serial_40004c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073774592 DT_N_S_soc_S_serial_40008000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073754112 DT_N_S_soc_S_watchdog_40003000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073753088 DT_N_S_soc_S_watchdog_40002c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073763328 DT_N_S_soc_S_i2c_40005400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073764352 DT_N_S_soc_S_i2c_40005800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073772544 DT_N_S_soc_S_i2c_40007800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073819648 DT_N_S_soc_S_spi_40013000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073756160 DT_N_S_soc_S_spi_40003800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073757184 DT_N_S_soc_S_spi_40003c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073767424 DT_N_S_soc_S_can_40006400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073773568 DT_N_S_soc_S_timers_40007c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073818624 DT_N_S_soc_S_timers_40012c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073741824 DT_N_S_soc_S_timers_40000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073742848 DT_N_S_soc_S_timers_40000400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073743872 DT_N_S_soc_S_timers_40000800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073745920 DT_N_S_soc_S_timers_40001000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073746944 DT_N_S_soc_S_timers_40001400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073820672 DT_N_S_soc_S_timers_40013400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073823744 DT_N_S_soc_S_timers_40014000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073824768 DT_N_S_soc_S_timers_40014400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073825792 DT_N_S_soc_S_timers_40014800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073752064 DT_N_S_soc_S_rtc_40002800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342572544 DT_N_S_soc_S_rng_50060800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073765376 DT_N_S_soc_S_usb_40005c00
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073872896 DT_N_S_soc_S_dma_40020000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073873920 DT_N_S_soc_S_dma_40020400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073874944 DT_N_S_soc_S_dmamux_40020800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073782784 DT_N_S_soc_S_ucpd_4000a000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073828868 DT_N_S_soc_S_sai1_40015404
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073828900 DT_N_S_soc_S_sai1_40015424
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073808128 DT_N_S_soc_S_opamp1_40010300
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073808132 DT_N_S_soc_S_opamp2_40010304
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073808136 DT_N_S_soc_S_opamp3_40010308
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073807872 DT_N_S_soc_S_comparator_40010200
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073807876 DT_N_S_soc_S_comparator_40010204
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1073885184 DT_N_S_soc_S_crc_40023000
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_adc_50000000) fn(DT_N_S_soc_S_adc_50000100) fn(DT_N_S_soc_S_dac_50000800) fn(DT_N_S_soc_S_dac_50001000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc_S_rcc_40021000) fn(DT_N_S_soc_S_interrupt_controller_40010400) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc_S_serial_40013800) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40008000) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_watchdog_40002c00) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40007800) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_can_40006400) fn(DT_N_S_soc_S_timers_40007c00) fn(DT_N_S_soc_S_timers_40012c00) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40013400) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_soc_S_usb_40005c00) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_ucpd_4000a000) fn(DT_N_S_soc_S_sai1_40015404) fn(DT_N_S_soc_S_sai1_40015424) fn(DT_N_S_soc_S_opamp1_40010300) fn(DT_N_S_soc_S_opamp2_40010304) fn(DT_N_S_soc_S_opamp3_40010308) fn(DT_N_S_soc_S_comparator_40010200) fn(DT_N_S_soc_S_comparator_40010204) fn(DT_N_S_soc_S_crc_40023000)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_50000100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_50000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_50001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40010400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40013800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40008000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40002c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40007800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40007c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40012c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40013400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40005c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_40020800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ucpd_4000a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015404) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015424) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_opamp1_40010300) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_opamp2_40010304) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_opamp3_40010308) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_comparator_40010200) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_comparator_40010204) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crc_40023000)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_adc_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_50000100, __VA_ARGS__) fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__) fn(DT_N_S_soc_S_dac_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40002c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_ucpd_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015404, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015424, __VA_ARGS__) fn(DT_N_S_soc_S_opamp1_40010300, __VA_ARGS__) fn(DT_N_S_soc_S_opamp2_40010304, __VA_ARGS__) fn(DT_N_S_soc_S_opamp3_40010308, __VA_ARGS__) fn(DT_N_S_soc_S_comparator_40010200, __VA_ARGS__) fn(DT_N_S_soc_S_comparator_40010204, __VA_ARGS__) fn(DT_N_S_soc_S_crc_40023000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_50000100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_50001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40002c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40007800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40012c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40013400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_40005c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ucpd_4000a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015404, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sai1_40015424, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_opamp1_40010300, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_opamp2_40010304, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_opamp3_40010308, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_comparator_40010200, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_comparator_40010204, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crc_40023000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_dac_50000800) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc_S_rcc_40021000) fn(DT_N_S_soc_S_interrupt_controller_40010400) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc_S_serial_40013800) fn(DT_N_S_soc_S_serial_40008000) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_timers_40007c00) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_rng_50060800)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_50000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40010400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40013800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40008000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40007c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_HASH DcVqqq9YzG86l3_Hk7pNncUh2rnHG8USjbVY6wBdFts

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 4
#define DT_N_S_soc_ORD_STR_SORTABLE 00004

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	10, /* /soc/adc@50000000 */ \
	11, /* /soc/flash-controller@40022000 */ \
	18, /* /soc/pin-controller@48000000 */ \
	21, /* /soc/i2c@40005400 */ \
	23, /* /soc/i2c@40005800 */ \
	25, /* /soc/i2c@40007800 */ \
	47, /* /soc/timers@40000000 */ \
	52, /* /soc/adc@50000100 */ \
	53, /* /soc/can@40006400 */ \
	54, /* /soc/comparator@40010200 */ \
	55, /* /soc/comparator@40010204 */ \
	56, /* /soc/crc@40023000 */ \
	58, /* /soc/dac@50000800 */ \
	59, /* /soc/dac@50001000 */ \
	60, /* /soc/dma@40020400 */ \
	61, /* /soc/dmamux@40020800 */ \
	62, /* /soc/interrupt-controller@40010400 */ \
	63, /* /soc/opamp1@40010300 */ \
	64, /* /soc/opamp2@40010304 */ \
	65, /* /soc/opamp3@40010308 */ \
	66, /* /soc/rng@50060800 */ \
	67, /* /soc/rtc@40002800 */ \
	68, /* /soc/dma@40020000 */ \
	69, /* /soc/sai1@40015404 */ \
	70, /* /soc/sai1@40015424 */ \
	71, /* /soc/serial@40004400 */ \
	72, /* /soc/serial@40004800 */ \
	73, /* /soc/serial@40004c00 */ \
	76, /* /soc/serial@40008000 */ \
	79, /* /soc/serial@40013800 */ \
	84, /* /soc/spi@40003800 */ \
	89, /* /soc/spi@40003c00 */ \
	94, /* /soc/spi@40013000 */ \
	95, /* /soc/timer@e000e010 */ \
	96, /* /soc/timers@40007c00 */ \
	97, /* /soc/ucpd@4000a000 */ \
	99, /* /soc/usb@40005c00 */ \
	100, /* /soc/watchdog@40002c00 */ \
	101, /* /soc/watchdog@40003000 */ \
	115, /* /soc/timers@40000400 */ \
	119, /* /soc/timers@40000800 */ \
	123, /* /soc/timers@40001000 */ \
	125, /* /soc/timers@40001400 */ \
	127, /* /soc/timers@40012c00 */ \
	131, /* /soc/timers@40013400 */ \
	135, /* /soc/timers@40014000 */ \
	138, /* /soc/timers@40014400 */ \
	141, /* /soc/timers@40014800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_st_stm32g431 DT_N_S_soc
#define DT_N_INST_0_st_stm32g4   DT_N_S_soc
#define DT_N_INST_0_simple_bus   DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_FOREACH_REG(fn) 
#define DT_N_S_soc_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_IRQ_LEVEL 0
#define DT_N_S_soc_COMPAT_MATCHES_st_stm32g431 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_0 "stm32g431"
#define DT_N_S_soc_COMPAT_MATCHES_st_stm32g4 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_1 "stm32g4"
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_ranges_EXISTS 1
#define DT_N_S_soc_P_compatible {"st,stm32g431", "st,stm32g4", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_0 "st,stm32g431"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g431
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN st_stm32g431
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G431
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "st,stm32g4"
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED st,stm32g4
#define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN st_stm32g4
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32G4
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
	fn(DT_N_S_soc, compatible, 1) \
	fn(DT_N_S_soc, compatible, 2)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 3
#define DT_N_S_soc_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v7m-nvic):
 *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UNQUOTED interrupt-controller@e000e100
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_TOKEN interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_E000E100

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_NODELABEL_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL(fn) fn(nvic)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_NODELABEL_VARGS(fn, ...) fn(nvic, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_HASH MNKByYDCdVxyLwiy4A_bv2jZfVhfDT01mZ2_1uEhUYQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 5
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00005

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	10, /* /soc/adc@50000000 */ \
	11, /* /soc/flash-controller@40022000 */ \
	21, /* /soc/i2c@40005400 */ \
	23, /* /soc/i2c@40005800 */ \
	25, /* /soc/i2c@40007800 */ \
	47, /* /soc/timers@40000000 */ \
	52, /* /soc/adc@50000100 */ \
	53, /* /soc/can@40006400 */ \
	54, /* /soc/comparator@40010200 */ \
	55, /* /soc/comparator@40010204 */ \
	60, /* /soc/dma@40020400 */ \
	61, /* /soc/dmamux@40020800 */ \
	62, /* /soc/interrupt-controller@40010400 */ \
	66, /* /soc/rng@50060800 */ \
	67, /* /soc/rtc@40002800 */ \
	68, /* /soc/dma@40020000 */ \
	71, /* /soc/serial@40004400 */ \
	72, /* /soc/serial@40004800 */ \
	73, /* /soc/serial@40004c00 */ \
	76, /* /soc/serial@40008000 */ \
	79, /* /soc/serial@40013800 */ \
	84, /* /soc/spi@40003800 */ \
	89, /* /soc/spi@40003c00 */ \
	94, /* /soc/spi@40013000 */ \
	96, /* /soc/timers@40007c00 */ \
	97, /* /soc/ucpd@4000a000 */ \
	99, /* /soc/usb@40005c00 */ \
	100, /* /soc/watchdog@40002c00 */ \
	115, /* /soc/timers@40000400 */ \
	119, /* /soc/timers@40000800 */ \
	123, /* /soc/timers@40001000 */ \
	125, /* /soc/timers@40001400 */ \
	127, /* /soc/timers@40012c00 */ \
	131, /* /soc/timers@40013400 */ \
	135, /* /soc/timers@40014000 */ \
	138, /* /soc/timers@40014400 */ \
	141, /* /soc/timers@40014800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v7m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_LEVEL 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v7m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v7m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 4
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v7m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v7m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v7m-nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v7m_nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V7M_NVIC
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_dma_coherent 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks
 *
 * Node identifier: DT_N_S_clocks
 */

/* Node's full path: */
#define DT_N_S_clocks_PATH "/clocks"

/* Node's name with unit-address: */
#define DT_N_S_clocks_FULL_NAME "clocks"
#define DT_N_S_clocks_FULL_NAME_UNQUOTED clocks
#define DT_N_S_clocks_FULL_NAME_TOKEN clocks
#define DT_N_S_clocks_FULL_NAME_UPPER_TOKEN CLOCKS

/* Node parent (/) identifier: */
#define DT_N_S_clocks_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_NODELABEL_NUM 0
#define DT_N_S_clocks_FOREACH_NODELABEL(fn) 
#define DT_N_S_clocks_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_clocks_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_CHILD_NUM 6
#define DT_N_S_clocks_CHILD_NUM_STATUS_OKAY 5
#define DT_N_S_clocks_FOREACH_CHILD(fn) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll)
#define DT_N_S_clocks_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi48) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll)
#define DT_N_S_clocks_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi48) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lse) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__)
#define DT_N_S_clocks_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks_S_pll, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_clocks_HASH 3P3fmk_q5wPvaymGA6NeomHHBb_cCfQX2PaKw_k1t_w

/* Node's dependency ordinal: */
#define DT_N_S_clocks_ORD 6
#define DT_N_S_clocks_ORD_STR_SORTABLE 00006

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_SUPPORTS_ORDS \
	7, /* /clocks/clk-hse */ \
	8, /* /clocks/pll */ \
	31, /* /clocks/clk-hsi */ \
	32, /* /clocks/clk-hsi48 */ \
	33, /* /clocks/clk-lse */ \
	34, /* /clocks/clk-lsi */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_REG_NUM 0
#define DT_N_S_clocks_FOREACH_REG(fn) 
#define DT_N_S_clocks_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_RANGES_NUM 0
#define DT_N_S_clocks_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_IRQ_NUM 0
#define DT_N_S_clocks_IRQ_LEVEL 0
#define DT_N_S_clocks_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /clocks/clk-hse
 *
 * Node identifier: DT_N_S_clocks_S_clk_hse
 *
 * Binding (compatible = st,stm32-hse-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/st,stm32-hse-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_hse_PATH "/clocks/clk-hse"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_hse_FULL_NAME "clk-hse"
#define DT_N_S_clocks_S_clk_hse_FULL_NAME_UNQUOTED clk-hse
#define DT_N_S_clocks_S_clk_hse_FULL_NAME_TOKEN clk_hse
#define DT_N_S_clocks_S_clk_hse_FULL_NAME_UPPER_TOKEN CLK_HSE

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_hse_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_hse_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_hse_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_hse_FOREACH_NODELABEL(fn) fn(clk_hse)
#define DT_N_S_clocks_S_clk_hse_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_hse, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_hse_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_hse_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_hse_HASH CHg50lhzojbh1fYYqBOhbjZFQvgn2_C8kiV4EgV0j3Y

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_hse_ORD 7
#define DT_N_S_clocks_S_clk_hse_ORD_STR_SORTABLE 00007

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_hse_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_hse_SUPPORTS_ORDS \
	8, /* /clocks/pll */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_hse_EXISTS 1
#define DT_N_INST_0_st_stm32_hse_clock DT_N_S_clocks_S_clk_hse
#define DT_N_NODELABEL_clk_hse         DT_N_S_clocks_S_clk_hse

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_hse_REG_NUM 0
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hse_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hse_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_hse_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_hse_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_hse_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_hse_COMPAT_MATCHES_st_stm32_hse_clock 1
#define DT_N_S_clocks_S_clk_hse_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_clk_hse_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_COMPAT_MODEL_IDX_0 "stm32-hse-clock"
#define DT_N_S_clocks_S_clk_hse_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_hse_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_hse_P_hse_bypass 0
#define DT_N_S_clocks_S_clk_hse_P_hse_bypass_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_css_enabled 0
#define DT_N_S_clocks_S_clk_hse_P_css_enabled_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_clock_frequency 24000000
#define DT_N_S_clocks_S_clk_hse_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status "okay"
#define DT_N_S_clocks_S_clk_hse_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_clk_hse_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_clk_hse_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hse, status, 0)
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse, status, 0)
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_status_LEN 1
#define DT_N_S_clocks_S_clk_hse_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_compatible {"st,stm32-hse-clock"}
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0 "st,stm32-hse-clock"
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-hse-clock
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_TOKEN st_stm32_hse_clock
#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_HSE_CLOCK
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hse, compatible, 0)
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse, compatible, 0)
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hse_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_hse_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_hse_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_hse_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_hse_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_hse_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_hse_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/pll
 *
 * Node identifier: DT_N_S_clocks_S_pll
 *
 * Binding (compatible = st,stm32g4-pll-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/st,stm32g4-pll-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_pll_PATH "/clocks/pll"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_pll_FULL_NAME "pll"
#define DT_N_S_clocks_S_pll_FULL_NAME_UNQUOTED pll
#define DT_N_S_clocks_S_pll_FULL_NAME_TOKEN pll
#define DT_N_S_clocks_S_pll_FULL_NAME_UPPER_TOKEN PLL

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_pll_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_pll_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_pll_NODELABEL_NUM 1
#define DT_N_S_clocks_S_pll_FOREACH_NODELABEL(fn) fn(pll)
#define DT_N_S_clocks_S_pll_FOREACH_NODELABEL_VARGS(fn, ...) fn(pll, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_pll_CHILD_NUM 0
#define DT_N_S_clocks_S_pll_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_pll_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_pll_HASH MENiPNxcjOF6dwaYSdS9Iq0tqHDbWKghVscDDRncn0o

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_pll_ORD 8
#define DT_N_S_clocks_S_pll_ORD_STR_SORTABLE 00008

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_pll_REQUIRES_ORDS \
	6, /* /clocks */ \
	7, /* /clocks/clk-hse */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_pll_SUPPORTS_ORDS \
	9, /* /soc/rcc@40021000 */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_pll_EXISTS 1
#define DT_N_INST_0_st_stm32g4_pll_clock DT_N_S_clocks_S_pll
#define DT_N_NODELABEL_pll               DT_N_S_clocks_S_pll

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_pll_REG_NUM 0
#define DT_N_S_clocks_S_pll_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_pll_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_pll_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_pll_RANGES_NUM 0
#define DT_N_S_clocks_S_pll_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_pll_IRQ_NUM 0
#define DT_N_S_clocks_S_pll_IRQ_LEVEL 0
#define DT_N_S_clocks_S_pll_COMPAT_MATCHES_st_stm32g4_pll_clock 1
#define DT_N_S_clocks_S_pll_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_pll_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_COMPAT_MODEL_IDX_0 "stm32g4-pll-clock"
#define DT_N_S_clocks_S_pll_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_pll_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_pll_P_div_m 6
#define DT_N_S_clocks_S_pll_P_div_m_EXISTS 1
#define DT_N_S_clocks_S_pll_P_mul_n 85
#define DT_N_S_clocks_S_pll_P_mul_n_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_p 7
#define DT_N_S_clocks_S_pll_P_div_p_EXISTS 1
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_PH DT_N_S_clocks_S_clk_hse
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_clocks_S_pll_P_clocks_IDX_0_NUM_CELLS 0
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll, clocks, 0)
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll, clocks, 0)
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll, clocks, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll, clocks, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_clocks_LEN 1
#define DT_N_S_clocks_S_pll_P_clocks_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_q 2
#define DT_N_S_clocks_S_pll_P_div_q_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_pll_P_div_q_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_q_IDX_0_ENUM_VAL_2_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_q_ENUM_VAL_2_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_q_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_r 2
#define DT_N_S_clocks_S_pll_P_div_r_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_pll_P_div_r_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_r_IDX_0_ENUM_VAL_2_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_r_ENUM_VAL_2_EXISTS 1
#define DT_N_S_clocks_S_pll_P_div_r_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status "okay"
#define DT_N_S_clocks_S_pll_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_pll_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_pll_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_pll_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_pll_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_pll_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll, status, 0)
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll, status, 0)
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_status_LEN 1
#define DT_N_S_clocks_S_pll_P_status_EXISTS 1
#define DT_N_S_clocks_S_pll_P_compatible {"st,stm32g4-pll-clock"}
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0 "st,stm32g4-pll-clock"
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g4-pll-clock
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_STRING_TOKEN st_stm32g4_pll_clock
#define DT_N_S_clocks_S_pll_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G4_PLL_CLOCK
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll, compatible, 0)
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll, compatible, 0)
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_pll_P_compatible_LEN 1
#define DT_N_S_clocks_S_pll_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_pll_P_dma_coherent 0
#define DT_N_S_clocks_S_pll_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_pll_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_pll_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_pll_P_wakeup_source 0
#define DT_N_S_clocks_S_pll_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_pll_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_pll_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rcc@40021000
 *
 * Node identifier: DT_N_S_soc_S_rcc_40021000
 *
 * Binding (compatible = st,stm32-rcc):
 *   $ZEPHYR_BASE/dts/bindings/clock/st,stm32-rcc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rcc_40021000_PATH "/soc/rcc@40021000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rcc_40021000_FULL_NAME "rcc@40021000"
#define DT_N_S_soc_S_rcc_40021000_FULL_NAME_UNQUOTED rcc@40021000
#define DT_N_S_soc_S_rcc_40021000_FULL_NAME_TOKEN rcc_40021000
#define DT_N_S_soc_S_rcc_40021000_FULL_NAME_UPPER_TOKEN RCC_40021000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rcc_40021000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rcc_40021000_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rcc_40021000_NODELABEL_NUM 1
#define DT_N_S_soc_S_rcc_40021000_FOREACH_NODELABEL(fn) fn(rcc)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rcc, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rcc_40021000_CHILD_NUM 1
#define DT_N_S_soc_S_rcc_40021000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_rcc_40021000_HASH 9dpgZGnFDhzfr3szN5sIDHeylLss1yadXzhaTcERMgU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rcc_40021000_ORD 9
#define DT_N_S_soc_S_rcc_40021000_ORD_STR_SORTABLE 00009

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rcc_40021000_REQUIRES_ORDS \
	4, /* /soc */ \
	8, /* /clocks/pll */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rcc_40021000_SUPPORTS_ORDS \
	10, /* /soc/adc@50000000 */ \
	11, /* /soc/flash-controller@40022000 */ \
	21, /* /soc/i2c@40005400 */ \
	23, /* /soc/i2c@40005800 */ \
	25, /* /soc/i2c@40007800 */ \
	40, /* /soc/pin-controller@48000000/gpio@48000800 */ \
	43, /* /soc/pin-controller@48000000/gpio@48000000 */ \
	46, /* /soc/rcc@40021000/reset-controller */ \
	47, /* /soc/timers@40000000 */ \
	52, /* /soc/adc@50000100 */ \
	53, /* /soc/can@40006400 */ \
	54, /* /soc/comparator@40010200 */ \
	55, /* /soc/comparator@40010204 */ \
	56, /* /soc/crc@40023000 */ \
	58, /* /soc/dac@50000800 */ \
	59, /* /soc/dac@50001000 */ \
	60, /* /soc/dma@40020400 */ \
	61, /* /soc/dmamux@40020800 */ \
	62, /* /soc/interrupt-controller@40010400 */ \
	63, /* /soc/opamp1@40010300 */ \
	64, /* /soc/opamp2@40010304 */ \
	65, /* /soc/opamp3@40010308 */ \
	66, /* /soc/rng@50060800 */ \
	67, /* /soc/rtc@40002800 */ \
	68, /* /soc/dma@40020000 */ \
	69, /* /soc/sai1@40015404 */ \
	70, /* /soc/sai1@40015424 */ \
	71, /* /soc/serial@40004400 */ \
	72, /* /soc/serial@40004800 */ \
	73, /* /soc/serial@40004c00 */ \
	76, /* /soc/serial@40008000 */ \
	79, /* /soc/serial@40013800 */ \
	84, /* /soc/spi@40003800 */ \
	89, /* /soc/spi@40003c00 */ \
	90, /* /soc/pin-controller@48000000/gpio@48000400 */ \
	94, /* /soc/spi@40013000 */ \
	96, /* /soc/timers@40007c00 */ \
	97, /* /soc/ucpd@4000a000 */ \
	99, /* /soc/usb@40005c00 */ \
	100, /* /soc/watchdog@40002c00 */ \
	109, /* /soc/pin-controller@48000000/gpio@48000c00 */ \
	110, /* /soc/pin-controller@48000000/gpio@48001000 */ \
	111, /* /soc/pin-controller@48000000/gpio@48001400 */ \
	112, /* /soc/pin-controller@48000000/gpio@48001800 */ \
	115, /* /soc/timers@40000400 */ \
	119, /* /soc/timers@40000800 */ \
	123, /* /soc/timers@40001000 */ \
	125, /* /soc/timers@40001400 */ \
	127, /* /soc/timers@40012c00 */ \
	131, /* /soc/timers@40013400 */ \
	135, /* /soc/timers@40014000 */ \
	138, /* /soc/timers@40014400 */ \
	141, /* /soc/timers@40014800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rcc_40021000_EXISTS 1
#define DT_N_INST_0_st_stm32_rcc DT_N_S_soc_S_rcc_40021000
#define DT_N_NODELABEL_rcc       DT_N_S_soc_S_rcc_40021000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rcc_40021000_REG_NUM 1
#define DT_N_S_soc_S_rcc_40021000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_REG_IDX_0_VAL_ADDRESS 1073876992 /* 0x40021000 */
#define DT_N_S_soc_S_rcc_40021000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_rcc_40021000_FOREACH_REG(fn) fn(DT_N_S_soc_S_rcc_40021000, 0)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40021000, 0)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40021000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40021000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_RANGES_NUM 0
#define DT_N_S_soc_S_rcc_40021000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rcc_40021000_IRQ_NUM 0
#define DT_N_S_soc_S_rcc_40021000_IRQ_LEVEL 0
#define DT_N_S_soc_S_rcc_40021000_COMPAT_MATCHES_st_stm32_rcc 1
#define DT_N_S_soc_S_rcc_40021000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rcc_40021000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_COMPAT_MODEL_IDX_0 "stm32-rcc"
#define DT_N_S_soc_S_rcc_40021000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rcc_40021000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rcc_40021000_P_reg {1073876992 /* 0x40021000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_rcc_40021000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_reg_IDX_0 1073876992
#define DT_N_S_soc_S_rcc_40021000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_rcc_40021000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_clock_frequency 170000000
#define DT_N_S_soc_S_rcc_40021000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_ahb_prescaler 1
#define DT_N_S_soc_S_rcc_40021000_P_ahb_prescaler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rcc_40021000_P_ahb_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_ahb_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_ahb_prescaler_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_ahb_prescaler_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb1_prescaler 1
#define DT_N_S_soc_S_rcc_40021000_P_apb1_prescaler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rcc_40021000_P_apb1_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb1_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb1_prescaler_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb1_prescaler_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb2_prescaler 1
#define DT_N_S_soc_S_rcc_40021000_P_apb2_prescaler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rcc_40021000_P_apb2_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb2_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb2_prescaler_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_apb2_prescaler_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_undershoot_prevention 1
#define DT_N_S_soc_S_rcc_40021000_P_undershoot_prevention_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_compatible {"st,stm32-rcc"}
#define DT_N_S_soc_S_rcc_40021000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_compatible_IDX_0 "st,stm32-rcc"
#define DT_N_S_soc_S_rcc_40021000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rcc
#define DT_N_S_soc_S_rcc_40021000_P_compatible_IDX_0_STRING_TOKEN st_stm32_rcc
#define DT_N_S_soc_S_rcc_40021000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RCC
#define DT_N_S_soc_S_rcc_40021000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_40021000, compatible, 0)
#define DT_N_S_soc_S_rcc_40021000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40021000, compatible, 0)
#define DT_N_S_soc_S_rcc_40021000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40021000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40021000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_P_compatible_LEN 1
#define DT_N_S_soc_S_rcc_40021000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_clocks_IDX_0_PH DT_N_S_clocks_S_pll
#define DT_N_S_soc_S_rcc_40021000_P_clocks_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_soc_S_rcc_40021000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40021000_P_clocks_IDX_0_NUM_CELLS 0
#define DT_N_S_soc_S_rcc_40021000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_40021000, clocks, 0)
#define DT_N_S_soc_S_rcc_40021000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40021000, clocks, 0)
#define DT_N_S_soc_S_rcc_40021000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40021000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40021000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_P_clocks_LEN 1
#define DT_N_S_soc_S_rcc_40021000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_dma_coherent 0
#define DT_N_S_soc_S_rcc_40021000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rcc_40021000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_wakeup_source 0
#define DT_N_S_soc_S_rcc_40021000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rcc_40021000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/adc@50000000
 *
 * Node identifier: DT_N_S_soc_S_adc_50000000
 *
 * Binding (compatible = st,stm32-adc):
 *   $ZEPHYR_BASE/dts/bindings/adc/st,stm32-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_50000000_PATH "/soc/adc@50000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_50000000_FULL_NAME "adc@50000000"
#define DT_N_S_soc_S_adc_50000000_FULL_NAME_UNQUOTED adc@50000000
#define DT_N_S_soc_S_adc_50000000_FULL_NAME_TOKEN adc_50000000
#define DT_N_S_soc_S_adc_50000000_FULL_NAME_UPPER_TOKEN ADC_50000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_50000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_50000000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_50000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_adc_50000000_FOREACH_NODELABEL(fn) fn(adc1)
#define DT_N_S_soc_S_adc_50000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_50000000_CHILD_NUM 0
#define DT_N_S_soc_S_adc_50000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_50000000_HASH sG6HR49ljr8TIUKEqdvb5cF7Fn342vIm_9put_XU4Bw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_50000000_ORD 10
#define DT_N_S_soc_S_adc_50000000_ORD_STR_SORTABLE 00010

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_50000000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_50000000_SUPPORTS_ORDS \
	16, /* /dietemp */ \
	28, /* /vbat */ \
	30, /* /vref */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_50000000_EXISTS 1
#define DT_N_INST_0_st_stm32_adc DT_N_S_soc_S_adc_50000000
#define DT_N_NODELABEL_adc1      DT_N_S_soc_S_adc_50000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_50000000_REG_NUM 1
#define DT_N_S_soc_S_adc_50000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_adc_50000000_REG_IDX_0_VAL_SIZE 256 /* 0x100 */
#define DT_N_S_soc_S_adc_50000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_50000000, 0)
#define DT_N_S_soc_S_adc_50000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, 0)
#define DT_N_S_soc_S_adc_50000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_RANGES_NUM 0
#define DT_N_S_soc_S_adc_50000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_50000000_IRQ_NUM 1
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_adc_50000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_adc_50000000_COMPAT_MATCHES_st_stm32_adc 1
#define DT_N_S_soc_S_adc_50000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_adc_50000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_COMPAT_MODEL_IDX_0 "stm32-adc"
#define DT_N_S_soc_S_adc_50000000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_50000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_50000000_P_reg {1342177280 /* 0x50000000 */, 256 /* 0x100 */}
#define DT_N_S_soc_S_adc_50000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_reg_IDX_0 1342177280
#define DT_N_S_soc_S_adc_50000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_reg_IDX_1 256
#define DT_N_S_soc_S_adc_50000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_VAL_bits 8192
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_50000000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_adc_50000000, clocks, 0, bits)
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, clocks, 0, bits)
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_NAME "adcx"
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_IDX 0
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_50000000, clocks, adcx, bus) \
	fn(DT_N_S_soc_S_adc_50000000, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, clocks, adcx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_NUM_CELLS 2
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_VAL_bus DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_VAL_bits DT_N_S_soc_S_adc_50000000_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_adc_50000000_P_clocks_NAME_adcx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, clocks, 0)
#define DT_N_S_soc_S_adc_50000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, clocks, 0)
#define DT_N_S_soc_S_adc_50000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clock_names {"adcx"}
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clock_names_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0 "adcx"
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0_STRING_UNQUOTED adcx
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0_STRING_TOKEN adcx
#define DT_N_S_soc_S_adc_50000000_P_clock_names_IDX_0_STRING_UPPER_TOKEN ADCX
#define DT_N_S_soc_S_adc_50000000_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, clock_names, 0)
#define DT_N_S_soc_S_adc_50000000_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, clock_names, 0)
#define DT_N_S_soc_S_adc_50000000_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_clock_names_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_adc_50000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_adc_50000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_adc_50000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_vref_mv 3300
#define DT_N_S_soc_S_adc_50000000_P_vref_mv_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions {12 /* 0xc */, 10 /* 0xa */, 8 /* 0x8 */, 6 /* 0x6 */}
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_0 12
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_1 10
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_2 8
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_IDX_3 6
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 0) \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 1) \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 2) \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_LEN 4
#define DT_N_S_soc_S_adc_50000000_P_st_adc_resolutions_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times {3 /* 0x3 */, 7 /* 0x7 */, 13 /* 0xd */, 25 /* 0x19 */, 48 /* 0x30 */, 93 /* 0x5d */, 248 /* 0xf8 */, 641 /* 0x281 */}
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_0 3
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_1 7
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_2 13
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_3 25
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_4_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_4 48
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_5_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_5 93
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_6_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_6 248
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_7_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_IDX_7 641
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, sampling_times, 0) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 1) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 2) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 3) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 4) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 5) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 6) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 7)
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 7)
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, sampling_times, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000000, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_LEN 8
#define DT_N_S_soc_S_adc_50000000_P_sampling_times_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer "programmable"
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_STRING_UNQUOTED programmable
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_STRING_TOKEN programmable
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_STRING_UPPER_TOKEN PROGRAMMABLE
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_IDX_0 "programmable"
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_IDX_0_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_sequencer_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler "minimal"
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_STRING_UNQUOTED minimal
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_STRING_TOKEN minimal
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_STRING_UPPER_TOKEN MINIMAL
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_IDX_0 "minimal"
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_IDX_0_ENUM_VAL_minimal_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_ENUM_VAL_minimal_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_oversampler_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator "startup-sw-delay"
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_STRING_UNQUOTED startup-sw-delay
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_STRING_TOKEN startup_sw_delay
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_STRING_UPPER_TOKEN STARTUP_SW_DELAY
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_IDX_0 "startup-sw-delay"
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_IDX_0_ENUM_VAL_startup_sw_delay_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_ENUM_VAL_startup_sw_delay_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_internal_regulator_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_deep_powerdown 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_deep_powerdown_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_channel_preselection 0
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_channel_preselection_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_differential_support 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_differential_support_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_injected_support 1
#define DT_N_S_soc_S_adc_50000000_P_st_adc_has_injected_support_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_status "disabled"
#define DT_N_S_soc_S_adc_50000000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_adc_50000000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_adc_50000000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_adc_50000000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_adc_50000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, status, 0)
#define DT_N_S_soc_S_adc_50000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, status, 0)
#define DT_N_S_soc_S_adc_50000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_status_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_compatible {"st,stm32-adc"}
#define DT_N_S_soc_S_adc_50000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_compatible_IDX_0 "st,stm32-adc"
#define DT_N_S_soc_S_adc_50000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc
#define DT_N_S_soc_S_adc_50000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc
#define DT_N_S_soc_S_adc_50000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC
#define DT_N_S_soc_S_adc_50000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000000, compatible, 0)
#define DT_N_S_soc_S_adc_50000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000000, compatible, 0)
#define DT_N_S_soc_S_adc_50000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000000_P_compatible_LEN 1
#define DT_N_S_soc_S_adc_50000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_dma_coherent 0
#define DT_N_S_soc_S_adc_50000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_50000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_wakeup_source 0
#define DT_N_S_soc_S_adc_50000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_50000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_50000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000
 *
 * Binding (compatible = st,stm32-flash-controller):
 *   $ZEPHYR_BASE/dts/bindings/flash_controller/st,stm32-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_PATH "/soc/flash-controller@40022000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_FULL_NAME "flash-controller@40022000"
#define DT_N_S_soc_S_flash_controller_40022000_FULL_NAME_UNQUOTED flash-controller@40022000
#define DT_N_S_soc_S_flash_controller_40022000_FULL_NAME_TOKEN flash_controller_40022000
#define DT_N_S_soc_S_flash_controller_40022000_FULL_NAME_UPPER_TOKEN FLASH_CONTROLLER_40022000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_NODELABEL(fn) fn(flash)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_CHILD_NUM 3
#define DT_N_S_soc_S_flash_controller_40022000_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_flash_controller_40022000_CHILD_UNIT_ADDR_INT_134217728 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_N_S_soc_S_flash_controller_40022000_CHILD_UNIT_ADDR_INT_536834048 DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000
#define DT_N_S_soc_S_flash_controller_40022000_CHILD_UNIT_ADDR_INT_536835328 DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_HASH zbmvNSGM4VOJM0v0g9IYHqSKWvouTrb8IP0EW85xJrs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_ORD 11
#define DT_N_S_soc_S_flash_controller_40022000_ORD_STR_SORTABLE 00011

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_SUPPORTS_ORDS \
	12, /* /soc/flash-controller@40022000/flash@1fff7500 */ \
	102, /* /soc/flash-controller@40022000/flash@1fff7000 */ \
	103, /* /soc/flash-controller@40022000/flash@8000000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_EXISTS 1
#define DT_N_INST_0_st_stm32_flash_controller   DT_N_S_soc_S_flash_controller_40022000
#define DT_N_INST_0_st_stm32g4_flash_controller DT_N_S_soc_S_flash_controller_40022000
#define DT_N_NODELABEL_flash                    DT_N_S_soc_S_flash_controller_40022000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_REG_IDX_0_VAL_ADDRESS 1073881088 /* 0x40022000 */
#define DT_N_S_soc_S_flash_controller_40022000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_VAL_irq 3
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_flash_controller_40022000_IRQ_LEVEL 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_MATCHES_st_stm32_flash_controller 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_MODEL_IDX_0 "stm32-flash-controller"
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_MATCHES_st_stm32g4_flash_controller 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_COMPAT_MODEL_IDX_1 "stm32g4-flash-controller"
#define DT_N_S_soc_S_flash_controller_40022000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_P_st_rdp1_enable_byte 85
#define DT_N_S_soc_S_flash_controller_40022000_P_st_rdp1_enable_byte_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_reg {1073881088 /* 0x40022000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_flash_controller_40022000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_reg_IDX_0 1073881088
#define DT_N_S_soc_S_flash_controller_40022000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_flash_controller_40022000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible {"st,stm32-flash-controller", "st,stm32g4-flash-controller"}
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_0 "st,stm32-flash-controller"
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-flash-controller
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_0_STRING_TOKEN st_stm32_flash_controller
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FLASH_CONTROLLER
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_1 "st,stm32g4-flash-controller"
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32g4-flash-controller
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_1_STRING_TOKEN st_stm32g4_flash_controller
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32G4_FLASH_CONTROLLER
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 0) \
	fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 1)
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 1)
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40022000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_LEN 2
#define DT_N_S_soc_S_flash_controller_40022000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_interrupts {3 /* 0x3 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_flash_controller_40022000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_interrupts_IDX_0 3
#define DT_N_S_soc_S_flash_controller_40022000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_flash_controller_40022000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_VAL_bus 72
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_VAL_bits 256
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0, bits)
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0, bits)
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0)
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0)
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@1fff7500
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500
 *
 * Binding (compatible = st,stm32-nvm-otp):
 *   $ZEPHYR_BASE/dts/bindings/otp/st,stm32-nvm-otp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_PATH "/soc/flash-controller@40022000/flash@1fff7500"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FULL_NAME "flash@1fff7500"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FULL_NAME_UNQUOTED flash@1fff7500
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FULL_NAME_TOKEN flash_1fff7500
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FULL_NAME_UPPER_TOKEN FLASH_1FFF7500

/* Node parent (/soc/flash-controller@40022000) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_PARENT DT_N_S_soc_S_flash_controller_40022000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_HASH yP8msK3Icm6hp_oROIPFyvpacEBcgNz1h7OlgsvRmfA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_ORD 12
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_ORD_STR_SORTABLE 00012

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_REQUIRES_ORDS \
	11, /* /soc/flash-controller@40022000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_SUPPORTS_ORDS \
	13, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_EXISTS 1
#define DT_N_INST_0_st_stm32_nvm_otp DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_REG_IDX_0_VAL_ADDRESS 536835328 /* 0x1fff7500 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_COMPAT_MATCHES_st_stm32_nvm_otp 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_COMPAT_MODEL_IDX_0 "stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_reg {536835328 /* 0x1fff7500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_reg_IDX_0 536835328
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_reg_IDX_1 768
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible {"st,stm32-nvm-otp"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_IDX_0 "st,stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-nvm-otp
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_IDX_0_STRING_TOKEN st_stm32_nvm_otp
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_NVM_OTP
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout
 *
 * Binding (compatible = fixed-layout):
 *   $ZEPHYR_BASE/dts/bindings/nvmem/fixed-layout.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_PATH "/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FULL_NAME "nvmem-layout"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FULL_NAME_UNQUOTED nvmem-layout
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FULL_NAME_TOKEN nvmem_layout
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FULL_NAME_UPPER_TOKEN NVMEM_LAYOUT

/* Node parent (/soc/flash-controller@40022000/flash@1fff7500) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_CHILD_NUM 3
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_CHILD_UNIT_ADDR_INT_168 DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_CHILD_UNIT_ADDR_INT_170 DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_CHILD_UNIT_ADDR_INT_202 DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_HASH d1P5penkKk2AjpB_MM7SstkYtJQgU_bilAjk8Xpdchs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_ORD 13
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_ORD_STR_SORTABLE 00013

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_REQUIRES_ORDS \
	12, /* /soc/flash-controller@40022000/flash@1fff7500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_SUPPORTS_ORDS \
	14, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal1@a8 */ \
	15, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal2@ca */ \
	29, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/vrefint@aa */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_EXISTS 1
#define DT_N_INST_0_fixed_layout DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_REG_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_REG(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_COMPAT_MATCHES_fixed_layout 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal1@a8
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_PATH "/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal1@a8"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FULL_NAME "ts-cal1@a8"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FULL_NAME_UNQUOTED ts-cal1@a8
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FULL_NAME_TOKEN ts_cal1_a8
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FULL_NAME_UPPER_TOKEN TS_CAL1_A8

/* Node parent (/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_NODELABEL(fn) fn(ts_cal1_otp)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_NODELABEL_VARGS(fn, ...) fn(ts_cal1_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_HASH IKf3UX_kp_ZY4j43xdbgTdgq6ftv7iEZ_U_qkaGAj_c

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_ORD 14
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_ORD_STR_SORTABLE 00014

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_REQUIRES_ORDS \
	13, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_SUPPORTS_ORDS \
	16, /* /dietemp */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_EXISTS 1
#define DT_N_NODELABEL_ts_cal1_otp DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_REG_IDX_0_VAL_ADDRESS 168 /* 0xa8 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_REG_IDX_0_VAL_SIZE 2 /* 0x2 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_reg {168 /* 0xa8 */, 2 /* 0x2 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_reg_IDX_0 168
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_reg_IDX_1 2
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8_P_read_only_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal2@ca
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_PATH "/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal2@ca"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FULL_NAME "ts-cal2@ca"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FULL_NAME_UNQUOTED ts-cal2@ca
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FULL_NAME_TOKEN ts_cal2_ca
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FULL_NAME_UPPER_TOKEN TS_CAL2_CA

/* Node parent (/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_NODELABEL(fn) fn(ts_cal2_otp)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_NODELABEL_VARGS(fn, ...) fn(ts_cal2_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_HASH MfhVDbSyzL_psu19u8q667uA_vvrq_DGXdK_gFm4F4s

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_ORD 15
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_ORD_STR_SORTABLE 00015

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_REQUIRES_ORDS \
	13, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_SUPPORTS_ORDS \
	16, /* /dietemp */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_EXISTS 1
#define DT_N_NODELABEL_ts_cal2_otp DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_REG_IDX_0_VAL_ADDRESS 202 /* 0xca */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_REG_IDX_0_VAL_SIZE 2 /* 0x2 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_reg {202 /* 0xca */, 2 /* 0x2 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_reg_IDX_0 202
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_reg_IDX_1 2
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca_P_read_only_EXISTS 1

/*
 * Devicetree node: /dietemp
 *
 * Node identifier: DT_N_S_dietemp
 *
 * Binding (compatible = st,stm32-temp-cal):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-temp-cal.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_dietemp_PATH "/dietemp"

/* Node's name with unit-address: */
#define DT_N_S_dietemp_FULL_NAME "dietemp"
#define DT_N_S_dietemp_FULL_NAME_UNQUOTED dietemp
#define DT_N_S_dietemp_FULL_NAME_TOKEN dietemp
#define DT_N_S_dietemp_FULL_NAME_UPPER_TOKEN DIETEMP

/* Node parent (/) identifier: */
#define DT_N_S_dietemp_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_dietemp_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_dietemp_NODELABEL_NUM 1
#define DT_N_S_dietemp_FOREACH_NODELABEL(fn) fn(die_temp)
#define DT_N_S_dietemp_FOREACH_NODELABEL_VARGS(fn, ...) fn(die_temp, __VA_ARGS__)
#define DT_N_S_dietemp_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_dietemp_CHILD_NUM 0
#define DT_N_S_dietemp_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_dietemp_FOREACH_CHILD(fn) 
#define DT_N_S_dietemp_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_dietemp_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_dietemp_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_dietemp_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_dietemp_HASH 1P3ft3QMjkFq1eBnbB6dz9pZsoSMwhVrPGe82Fpxz6c

/* Node's dependency ordinal: */
#define DT_N_S_dietemp_ORD 16
#define DT_N_S_dietemp_ORD_STR_SORTABLE 00016

/* Ordinals for what this node depends on directly: */
#define DT_N_S_dietemp_REQUIRES_ORDS \
	0, /* / */ \
	10, /* /soc/adc@50000000 */ \
	14, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal1@a8 */ \
	15, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/ts-cal2@ca */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_dietemp_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_dietemp_EXISTS 1
#define DT_N_INST_0_st_stm32_temp_cal DT_N_S_dietemp
#define DT_N_NODELABEL_die_temp       DT_N_S_dietemp

/* Macros for properties that are special in the specification: */
#define DT_N_S_dietemp_REG_NUM 0
#define DT_N_S_dietemp_FOREACH_REG(fn) 
#define DT_N_S_dietemp_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_dietemp_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_dietemp_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_dietemp_RANGES_NUM 0
#define DT_N_S_dietemp_FOREACH_RANGE(fn) 
#define DT_N_S_dietemp_IRQ_NUM 0
#define DT_N_S_dietemp_IRQ_LEVEL 0
#define DT_N_S_dietemp_COMPAT_MATCHES_st_stm32_temp_cal 1
#define DT_N_S_dietemp_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_dietemp_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_dietemp_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_dietemp_COMPAT_MODEL_IDX_0 "stm32-temp-cal"
#define DT_N_S_dietemp_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_dietemp_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_dietemp_P_nvmem_cell_names {"TS_CAL1", "TS_CAL2"}
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_ENUM_IDX 0
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_ENUM_IDX 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_ENUM_VAL_ts_cal1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_ENUM_VAL_ts_cal1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_ENUM_VAL_ts_cal2_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_ENUM_VAL_ts_cal2_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0 "TS_CAL1"
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_STRING_UNQUOTED TS_CAL1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_STRING_TOKEN TS_CAL1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_0_STRING_UPPER_TOKEN TS_CAL1
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1 "TS_CAL2"
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_STRING_UNQUOTED TS_CAL2
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_STRING_TOKEN TS_CAL2
#define DT_N_S_dietemp_P_nvmem_cell_names_IDX_1_STRING_UPPER_TOKEN TS_CAL2
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, nvmem_cell_names, 0) \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1)
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, nvmem_cell_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1)
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, nvmem_cell_names, 0, __VA_ARGS__) \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cell_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, nvmem_cell_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cell_names, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cell_names_LEN 2
#define DT_N_S_dietemp_P_nvmem_cell_names_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal2_temp 130
#define DT_N_S_dietemp_P_ts_cal2_temp_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_PH DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_IDX_0_NAME "TS_CAL1"
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_IDX 0
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_PH DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_PH DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_IDX_1_NAME "TS_CAL2"
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_IDX 1
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_FOREACH_CELL(fn) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_NUM_CELLS 0
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_PH DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca
#define DT_N_S_dietemp_P_nvmem_cells_NAME_ts_cal2_EXISTS 1
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, nvmem_cells, 0) \
	fn(DT_N_S_dietemp, nvmem_cells, 1)
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, nvmem_cells, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cells, 1)
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, nvmem_cells, 0, __VA_ARGS__) \
	fn(DT_N_S_dietemp, nvmem_cells, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cells_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, nvmem_cells, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_dietemp, nvmem_cells, 1, __VA_ARGS__)
#define DT_N_S_dietemp_P_nvmem_cells_LEN 2
#define DT_N_S_dietemp_P_nvmem_cells_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal1_temp 30
#define DT_N_S_dietemp_P_ts_cal1_temp_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_vrefanalog 3000
#define DT_N_S_dietemp_P_ts_cal_vrefanalog_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution 12
#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_ENUM_IDX 0
#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_ENUM_VAL_12_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution_ENUM_VAL_12_EXISTS 1
#define DT_N_S_dietemp_P_ts_cal_resolution_EXISTS 1
#define DT_N_S_dietemp_P_status "disabled"
#define DT_N_S_dietemp_P_status_STRING_UNQUOTED disabled
#define DT_N_S_dietemp_P_status_STRING_TOKEN disabled
#define DT_N_S_dietemp_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_dietemp_P_status_IDX_0 "disabled"
#define DT_N_S_dietemp_P_status_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_dietemp_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_dietemp_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, status, 0)
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, status, 0)
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, status, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, status, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_status_LEN 1
#define DT_N_S_dietemp_P_status_EXISTS 1
#define DT_N_S_dietemp_P_compatible {"st,stm32-temp-cal"}
#define DT_N_S_dietemp_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_compatible_IDX_0 "st,stm32-temp-cal"
#define DT_N_S_dietemp_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-temp-cal
#define DT_N_S_dietemp_P_compatible_IDX_0_STRING_TOKEN st_stm32_temp_cal
#define DT_N_S_dietemp_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TEMP_CAL
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, compatible, 0)
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, compatible, 0)
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, compatible, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, compatible, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_compatible_LEN 1
#define DT_N_S_dietemp_P_compatible_EXISTS 1
#define DT_N_S_dietemp_P_dma_coherent 0
#define DT_N_S_dietemp_P_dma_coherent_EXISTS 1
#define DT_N_S_dietemp_P_io_channels_IDX_0_EXISTS 1
#define DT_N_S_dietemp_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_50000000
#define DT_N_S_dietemp_P_io_channels_IDX_0_VAL_input 16
#define DT_N_S_dietemp_P_io_channels_IDX_0_VAL_input_EXISTS 1
#define DT_N_S_dietemp_P_io_channels_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_dietemp, io_channels, 0, input)
#define DT_N_S_dietemp_P_io_channels_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_dietemp, io_channels, 0, input)
#define DT_N_S_dietemp_P_io_channels_IDX_0_NUM_CELLS 1
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, io_channels, 0)
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, io_channels, 0)
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, io_channels, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_dietemp, io_channels, 0, __VA_ARGS__)
#define DT_N_S_dietemp_P_io_channels_LEN 1
#define DT_N_S_dietemp_P_io_channels_EXISTS 1
#define DT_N_S_dietemp_P_zephyr_deferred_init 0
#define DT_N_S_dietemp_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_dietemp_P_wakeup_source 0
#define DT_N_S_dietemp_P_wakeup_source_EXISTS 1
#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /memory@20000000
 *
 * Node identifier: DT_N_S_memory_20000000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_memory_20000000_PATH "/memory@20000000"

/* Node's name with unit-address: */
#define DT_N_S_memory_20000000_FULL_NAME "memory@20000000"
#define DT_N_S_memory_20000000_FULL_NAME_UNQUOTED memory@20000000
#define DT_N_S_memory_20000000_FULL_NAME_TOKEN memory_20000000
#define DT_N_S_memory_20000000_FULL_NAME_UPPER_TOKEN MEMORY_20000000

/* Node parent (/) identifier: */
#define DT_N_S_memory_20000000_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_memory_20000000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_memory_20000000_NODELABEL_NUM 1
#define DT_N_S_memory_20000000_FOREACH_NODELABEL(fn) fn(sram0)
#define DT_N_S_memory_20000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0, __VA_ARGS__)
#define DT_N_S_memory_20000000_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_memory_20000000_CHILD_NUM 0
#define DT_N_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_memory_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_memory_20000000_HASH Ppv28MrjF0V_ocFctWWy62TJJRdbnlSCTerwKpAvZ6U

/* Node's dependency ordinal: */
#define DT_N_S_memory_20000000_ORD 17
#define DT_N_S_memory_20000000_ORD_STR_SORTABLE 00017

/* Ordinals for what this node depends on directly: */
#define DT_N_S_memory_20000000_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_zephyr_memory_region DT_N_S_memory_20000000
#define DT_N_INST_0_mmio_sram            DT_N_S_memory_20000000
#define DT_N_NODELABEL_sram0             DT_N_S_memory_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_memory_20000000_REG_NUM 1
#define DT_N_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_memory_20000000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_memory_20000000_FOREACH_REG(fn) fn(DT_N_S_memory_20000000, 0)
#define DT_N_S_memory_20000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_memory_20000000, 0)
#define DT_N_S_memory_20000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_memory_20000000, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_20000000, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_RANGES_NUM 0
#define DT_N_S_memory_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_memory_20000000_IRQ_LEVEL 0
#define DT_N_S_memory_20000000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_memory_20000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_memory_20000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_memory_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_memory_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_memory_20000000_P_zephyr_memory_region "SRAM0"
#define DT_N_S_memory_20000000_P_zephyr_memory_region_STRING_UNQUOTED SRAM0
#define DT_N_S_memory_20000000_P_zephyr_memory_region_STRING_TOKEN SRAM0
#define DT_N_S_memory_20000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM0
#define DT_N_S_memory_20000000_P_zephyr_memory_region_IDX_0 "SRAM0"
#define DT_N_S_memory_20000000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_20000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_zephyr_memory_region_LEN 1
#define DT_N_S_memory_20000000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_memory_20000000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_memory_20000000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_memory_20000000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_memory_20000000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_memory_20000000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_memory_20000000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_20000000, compatible, 0) \
	fn(DT_N_S_memory_20000000, compatible, 1)
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_20000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_memory_20000000, compatible, 1)
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_20000000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_memory_20000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_20000000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_memory_20000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_memory_20000000_P_compatible_LEN 2
#define DT_N_S_memory_20000000_P_compatible_EXISTS 1
#define DT_N_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 32768 /* 0x8000 */}
#define DT_N_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_memory_20000000_P_reg_IDX_1 32768
#define DT_N_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_memory_20000000_P_dma_coherent 0
#define DT_N_S_memory_20000000_P_dma_coherent_EXISTS 1
#define DT_N_S_memory_20000000_P_zephyr_deferred_init 0
#define DT_N_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_memory_20000000_P_wakeup_source 0
#define DT_N_S_memory_20000000_P_wakeup_source_EXISTS 1
#define DT_N_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000
 *
 * Binding (compatible = st,stm32-pinctrl):
 *   $ZEPHYR_BASE/dts/bindings/pinctrl/st,stm32-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_PATH "/soc/pin-controller@48000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_FULL_NAME "pin-controller@48000000"
#define DT_N_S_soc_S_pin_controller_48000000_FULL_NAME_UNQUOTED pin-controller@48000000
#define DT_N_S_soc_S_pin_controller_48000000_FULL_NAME_TOKEN pin_controller_48000000
#define DT_N_S_soc_S_pin_controller_48000000_FULL_NAME_UPPER_TOKEN PIN_CONTROLLER_48000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_NODELABEL(fn) fn(pinctrl)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_NUM 26
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_NUM_STATUS_OKAY 26
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207959552 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207960576 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207961600 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207962624 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207963648 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207964672 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400
#define DT_N_S_soc_S_pin_controller_48000000_CHILD_UNIT_ADDR_INT_1207965696 DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_HASH t9nOZVnIU1TMOZorPnXPYV59gij_PefzrEfm0_7N_5g

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_ORD 18
#define DT_N_S_soc_S_pin_controller_48000000_ORD_STR_SORTABLE 00018

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_SUPPORTS_ORDS \
	19, /* /soc/pin-controller@48000000/i2c1_scl_pb8 */ \
	20, /* /soc/pin-controller@48000000/i2c1_sda_pb9 */ \
	40, /* /soc/pin-controller@48000000/gpio@48000800 */ \
	43, /* /soc/pin-controller@48000000/gpio@48000000 */ \
	48, /* /soc/pin-controller@48000000/tim2_ch1_pa5 */ \
	57, /* /soc/pin-controller@48000000/dac1_out1_pa4 */ \
	74, /* /soc/pin-controller@48000000/lpuart1_rx_pa3 */ \
	75, /* /soc/pin-controller@48000000/lpuart1_tx_pa2 */ \
	77, /* /soc/pin-controller@48000000/usart1_rx_pc5 */ \
	78, /* /soc/pin-controller@48000000/usart1_tx_pc4 */ \
	80, /* /soc/pin-controller@48000000/spi2_miso_pb14 */ \
	81, /* /soc/pin-controller@48000000/spi2_mosi_pb15 */ \
	82, /* /soc/pin-controller@48000000/spi2_nss_pb12 */ \
	83, /* /soc/pin-controller@48000000/spi2_sck_pb13 */ \
	85, /* /soc/pin-controller@48000000/spi3_miso_pc11 */ \
	86, /* /soc/pin-controller@48000000/spi3_mosi_pc12 */ \
	87, /* /soc/pin-controller@48000000/spi3_nss_pa15 */ \
	88, /* /soc/pin-controller@48000000/spi3_sck_pc10 */ \
	90, /* /soc/pin-controller@48000000/gpio@48000400 */ \
	91, /* /soc/pin-controller@48000000/spi1_miso_pa6 */ \
	92, /* /soc/pin-controller@48000000/spi1_mosi_pa7 */ \
	93, /* /soc/pin-controller@48000000/spi1_sck_pa5 */ \
	109, /* /soc/pin-controller@48000000/gpio@48000c00 */ \
	110, /* /soc/pin-controller@48000000/gpio@48001000 */ \
	111, /* /soc/pin-controller@48000000/gpio@48001400 */ \
	112, /* /soc/pin-controller@48000000/gpio@48001800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_EXISTS 1
#define DT_N_INST_0_st_stm32_pinctrl DT_N_S_soc_S_pin_controller_48000000
#define DT_N_NODELABEL_pinctrl       DT_N_S_soc_S_pin_controller_48000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_REG_IDX_0_VAL_ADDRESS 1207959552 /* 0x48000000 */
#define DT_N_S_soc_S_pin_controller_48000000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000, 0)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000, 0)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_COMPAT_MATCHES_st_stm32_pinctrl 1
#define DT_N_S_soc_S_pin_controller_48000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_COMPAT_MODEL_IDX_0 "stm32-pinctrl"
#define DT_N_S_soc_S_pin_controller_48000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_P_reg {1207959552 /* 0x48000000 */, 8192 /* 0x2000 */}
#define DT_N_S_soc_S_pin_controller_48000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_reg_IDX_0 1207959552
#define DT_N_S_soc_S_pin_controller_48000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_reg_IDX_1 8192
#define DT_N_S_soc_S_pin_controller_48000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_remap_pa11 0
#define DT_N_S_soc_S_pin_controller_48000000_P_remap_pa11_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_remap_pa12 0
#define DT_N_S_soc_S_pin_controller_48000000_P_remap_pa12_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_remap_pa11_pa12 0
#define DT_N_S_soc_S_pin_controller_48000000_P_remap_pa11_pa12_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible {"st,stm32-pinctrl"}
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_IDX_0 "st,stm32-pinctrl"
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pinctrl
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_pinctrl
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PINCTRL
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/i2c1_scl_pb8
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_PATH "/soc/pin-controller@48000000/i2c1_scl_pb8"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FULL_NAME "i2c1_scl_pb8"
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FULL_NAME_UNQUOTED i2c1_scl_pb8
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FULL_NAME_TOKEN i2c1_scl_pb8
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FULL_NAME_UPPER_TOKEN I2C1_SCL_PB8

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_NODELABEL(fn) fn(i2c1_scl_pb8)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_scl_pb8, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_HASH 0FQ7pQXkOFsPWL84dNECQjIA_ud_vczsOsQ64ys5dkw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_ORD 19
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_ORD_STR_SORTABLE 00019

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_SUPPORTS_ORDS \
	21, /* /soc/i2c@40005400 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_EXISTS 1
#define DT_N_NODELABEL_i2c1_scl_pb8 DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_pinmux 772
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_drive_open_drain 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/i2c1_sda_pb9
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_PATH "/soc/pin-controller@48000000/i2c1_sda_pb9"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FULL_NAME "i2c1_sda_pb9"
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FULL_NAME_UNQUOTED i2c1_sda_pb9
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FULL_NAME_TOKEN i2c1_sda_pb9
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FULL_NAME_UPPER_TOKEN I2C1_SDA_PB9

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_NODELABEL(fn) fn(i2c1_sda_pb9)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_sda_pb9, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_HASH URBomKZmBax9q1m2LG44r87TSG3tpy9qBVZ5LUCaDrc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_ORD 20
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_ORD_STR_SORTABLE 00020

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_SUPPORTS_ORDS \
	21, /* /soc/i2c@40005400 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_EXISTS 1
#define DT_N_NODELABEL_i2c1_sda_pb9 DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_pinmux 804
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_drive_open_drain 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40005400
 *
 * Node identifier: DT_N_S_soc_S_i2c_40005400
 *
 * Binding (compatible = st,stm32-i2c-v2):
 *   $ZEPHYR_BASE/dts/bindings/i2c/st,stm32-i2c-v2.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40005400_PATH "/soc/i2c@40005400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME "i2c@40005400"
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_UNQUOTED i2c@40005400
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_TOKEN i2c_40005400
#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_UPPER_TOKEN I2C_40005400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40005400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40005400_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_40005400_NODELABEL_NUM 2
#define DT_N_S_soc_S_i2c_40005400_FOREACH_NODELABEL(fn) fn(i2c1) fn(arduino_i2c)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1, __VA_ARGS__) fn(arduino_i2c, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40005400_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40005400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_40005400_HASH qdcoGqslkp_qGZ59SAaN4H47YRea2PU_8MI_v34YdEo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40005400_ORD 21
#define DT_N_S_soc_S_i2c_40005400_ORD_STR_SORTABLE 00021

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40005400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	19, /* /soc/pin-controller@48000000/i2c1_scl_pb8 */ \
	20, /* /soc/pin-controller@48000000/i2c1_sda_pb9 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40005400_SUPPORTS_ORDS \
	22, /* /smbus1 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40005400_EXISTS 1
#define DT_N_INST_0_st_stm32_i2c_v2 DT_N_S_soc_S_i2c_40005400
#define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_i2c_40005400
#define DT_N_NODELABEL_arduino_i2c  DT_N_S_soc_S_i2c_40005400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40005400_REG_NUM 1
#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_ADDRESS 1073763328 /* 0x40005400 */
#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_40005400, 0)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, 0)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40005400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40005400_IRQ_NUM 2
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_irq 32
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005400_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_irq DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_priority DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_event_CONTROLLER DT_N_S_soc_S_i2c_40005400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_irq DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_priority DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_IRQ_NAME_error_CONTROLLER DT_N_S_soc_S_i2c_40005400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_i2c_40005400_COMPAT_MATCHES_st_stm32_i2c_v2 1
#define DT_N_S_soc_S_i2c_40005400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2c_40005400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_COMPAT_MODEL_IDX_0 "stm32-i2c-v2"
#define DT_N_S_soc_S_i2c_40005400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NUM 1
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8
#define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40005400_P_reg {1073763328 /* 0x40005400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0 1073763328
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2c_40005400_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts {31 /* 0x1f */, 0 /* 0x0 */, 32 /* 0x20 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2 32
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_i2c_40005400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_sq_size 4
#define DT_N_S_soc_S_i2c_40005400_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_cq_size 4
#define DT_N_S_soc_S_i2c_40005400_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status "okay"
#define DT_N_S_soc_S_i2c_40005400_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_i2c_40005400_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_i2c_40005400_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, status, 0)
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, status, 0)
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_compatible {"st,stm32-i2c-v2"}
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0 "st,stm32-i2c-v2"
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2
#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names {"event", "error"}
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0 "event"
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_UNQUOTED event
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_TOKEN event
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1 "error"
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_UNQUOTED error
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_TOKEN error
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bits 2097152
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005400_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_40005400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_dma_coherent 0
#define DT_N_S_soc_S_i2c_40005400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /smbus1
 *
 * Node identifier: DT_N_S_smbus1
 *
 * Binding (compatible = st,stm32-smbus):
 *   $ZEPHYR_BASE/dts/bindings/smbus/st,stm32-smbus.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_smbus1_PATH "/smbus1"

/* Node's name with unit-address: */
#define DT_N_S_smbus1_FULL_NAME "smbus1"
#define DT_N_S_smbus1_FULL_NAME_UNQUOTED smbus1
#define DT_N_S_smbus1_FULL_NAME_TOKEN smbus1
#define DT_N_S_smbus1_FULL_NAME_UPPER_TOKEN SMBUS1

/* Node parent (/) identifier: */
#define DT_N_S_smbus1_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_smbus1_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_smbus1_NODELABEL_NUM 1
#define DT_N_S_smbus1_FOREACH_NODELABEL(fn) fn(smbus1)
#define DT_N_S_smbus1_FOREACH_NODELABEL_VARGS(fn, ...) fn(smbus1, __VA_ARGS__)
#define DT_N_S_smbus1_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_smbus1_CHILD_NUM 0
#define DT_N_S_smbus1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_smbus1_FOREACH_CHILD(fn) 
#define DT_N_S_smbus1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_smbus1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_smbus1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_smbus1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_smbus1_HASH RRjxCtQo8vEaNES3pUGCHfX2Mp6H0kS5wnsZuRpKBrY

/* Node's dependency ordinal: */
#define DT_N_S_smbus1_ORD 22
#define DT_N_S_smbus1_ORD_STR_SORTABLE 00022

/* Ordinals for what this node depends on directly: */
#define DT_N_S_smbus1_REQUIRES_ORDS \
	0, /* / */ \
	21, /* /soc/i2c@40005400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_smbus1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_smbus1_EXISTS 1
#define DT_N_INST_0_st_stm32_smbus DT_N_S_smbus1
#define DT_N_NODELABEL_smbus1      DT_N_S_smbus1

/* Macros for properties that are special in the specification: */
#define DT_N_S_smbus1_REG_NUM 0
#define DT_N_S_smbus1_FOREACH_REG(fn) 
#define DT_N_S_smbus1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_smbus1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_smbus1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus1_RANGES_NUM 0
#define DT_N_S_smbus1_FOREACH_RANGE(fn) 
#define DT_N_S_smbus1_IRQ_NUM 0
#define DT_N_S_smbus1_IRQ_LEVEL 0
#define DT_N_S_smbus1_COMPAT_MATCHES_st_stm32_smbus 1
#define DT_N_S_smbus1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_smbus1_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_smbus1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_smbus1_COMPAT_MODEL_IDX_0 "stm32-smbus"
#define DT_N_S_smbus1_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_smbus1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_smbus1_P_i2c DT_N_S_soc_S_i2c_40005400
#define DT_N_S_smbus1_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005400
#define DT_N_S_smbus1_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005400
#define DT_N_S_smbus1_P_i2c_IDX_0_EXISTS 1
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, i2c, 0)
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, i2c, 0)
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_i2c_LEN 1
#define DT_N_S_smbus1_P_i2c_EXISTS 1
#define DT_N_S_smbus1_P_status "disabled"
#define DT_N_S_smbus1_P_status_STRING_UNQUOTED disabled
#define DT_N_S_smbus1_P_status_STRING_TOKEN disabled
#define DT_N_S_smbus1_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_smbus1_P_status_IDX_0 "disabled"
#define DT_N_S_smbus1_P_status_IDX_0_EXISTS 1
#define DT_N_S_smbus1_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_smbus1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus1_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, status, 0)
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, status, 0)
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, status, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, status, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_status_LEN 1
#define DT_N_S_smbus1_P_status_EXISTS 1
#define DT_N_S_smbus1_P_compatible {"st,stm32-smbus"}
#define DT_N_S_smbus1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_smbus1_P_compatible_IDX_0 "st,stm32-smbus"
#define DT_N_S_smbus1_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus
#define DT_N_S_smbus1_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus
#define DT_N_S_smbus1_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, compatible, 0)
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, compatible, 0)
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus1_P_compatible_LEN 1
#define DT_N_S_smbus1_P_compatible_EXISTS 1
#define DT_N_S_smbus1_P_dma_coherent 0
#define DT_N_S_smbus1_P_dma_coherent_EXISTS 1
#define DT_N_S_smbus1_P_zephyr_deferred_init 0
#define DT_N_S_smbus1_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_smbus1_P_wakeup_source 0
#define DT_N_S_smbus1_P_wakeup_source_EXISTS 1
#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40005800
 *
 * Node identifier: DT_N_S_soc_S_i2c_40005800
 *
 * Binding (compatible = st,stm32-i2c-v2):
 *   $ZEPHYR_BASE/dts/bindings/i2c/st,stm32-i2c-v2.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40005800_PATH "/soc/i2c@40005800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME "i2c@40005800"
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_UNQUOTED i2c@40005800
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_TOKEN i2c_40005800
#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_UPPER_TOKEN I2C_40005800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40005800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40005800_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_40005800_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2c_40005800_FOREACH_NODELABEL(fn) fn(i2c2)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c2, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40005800_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40005800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40005800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_40005800_HASH eB73TQqq_PUOgKTcnvcwzuS4tWCFU0fUXyPb0bwWGkQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40005800_ORD 23
#define DT_N_S_soc_S_i2c_40005800_ORD_STR_SORTABLE 00023

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40005800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40005800_SUPPORTS_ORDS \
	24, /* /smbus2 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40005800_EXISTS 1
#define DT_N_INST_1_st_stm32_i2c_v2 DT_N_S_soc_S_i2c_40005800
#define DT_N_NODELABEL_i2c2         DT_N_S_soc_S_i2c_40005800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40005800_REG_NUM 1
#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_ADDRESS 1073764352 /* 0x40005800 */
#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_40005800, 0)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, 0)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40005800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40005800_IRQ_NUM 2
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_irq 34
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40005800_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_irq DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_priority DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_event_CONTROLLER DT_N_S_soc_S_i2c_40005800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_irq DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_priority DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_IRQ_NAME_error_CONTROLLER DT_N_S_soc_S_i2c_40005800_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_i2c_40005800_COMPAT_MATCHES_st_stm32_i2c_v2 1
#define DT_N_S_soc_S_i2c_40005800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2c_40005800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_COMPAT_MODEL_IDX_0 "stm32-i2c-v2"
#define DT_N_S_soc_S_i2c_40005800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40005800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40005800_P_reg {1073764352 /* 0x40005800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0 1073764352
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2c_40005800_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts {33 /* 0x21 */, 0 /* 0x0 */, 34 /* 0x22 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2 34
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_i2c_40005800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_sq_size 4
#define DT_N_S_soc_S_i2c_40005800_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_cq_size 4
#define DT_N_S_soc_S_i2c_40005800_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status "disabled"
#define DT_N_S_soc_S_i2c_40005800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2c_40005800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2c_40005800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, status, 0)
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, status, 0)
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_compatible {"st,stm32-i2c-v2"}
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0 "st,stm32-i2c-v2"
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2
#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names {"event", "error"}
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0 "event"
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_UNQUOTED event
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_TOKEN event
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1 "error"
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_UNQUOTED error
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_TOKEN error
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0) \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bits 4194304
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40005800_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_40005800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_dma_coherent 0
#define DT_N_S_soc_S_i2c_40005800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /smbus2
 *
 * Node identifier: DT_N_S_smbus2
 *
 * Binding (compatible = st,stm32-smbus):
 *   $ZEPHYR_BASE/dts/bindings/smbus/st,stm32-smbus.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_smbus2_PATH "/smbus2"

/* Node's name with unit-address: */
#define DT_N_S_smbus2_FULL_NAME "smbus2"
#define DT_N_S_smbus2_FULL_NAME_UNQUOTED smbus2
#define DT_N_S_smbus2_FULL_NAME_TOKEN smbus2
#define DT_N_S_smbus2_FULL_NAME_UPPER_TOKEN SMBUS2

/* Node parent (/) identifier: */
#define DT_N_S_smbus2_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_smbus2_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_smbus2_NODELABEL_NUM 1
#define DT_N_S_smbus2_FOREACH_NODELABEL(fn) fn(smbus2)
#define DT_N_S_smbus2_FOREACH_NODELABEL_VARGS(fn, ...) fn(smbus2, __VA_ARGS__)
#define DT_N_S_smbus2_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_smbus2_CHILD_NUM 0
#define DT_N_S_smbus2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_smbus2_FOREACH_CHILD(fn) 
#define DT_N_S_smbus2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_smbus2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_smbus2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_smbus2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_smbus2_HASH CeKsUeBLVHACPFrmleKnxYHTPUYQ02SrNC2w1a_Vmm4

/* Node's dependency ordinal: */
#define DT_N_S_smbus2_ORD 24
#define DT_N_S_smbus2_ORD_STR_SORTABLE 00024

/* Ordinals for what this node depends on directly: */
#define DT_N_S_smbus2_REQUIRES_ORDS \
	0, /* / */ \
	23, /* /soc/i2c@40005800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_smbus2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_smbus2_EXISTS 1
#define DT_N_INST_1_st_stm32_smbus DT_N_S_smbus2
#define DT_N_NODELABEL_smbus2      DT_N_S_smbus2

/* Macros for properties that are special in the specification: */
#define DT_N_S_smbus2_REG_NUM 0
#define DT_N_S_smbus2_FOREACH_REG(fn) 
#define DT_N_S_smbus2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_smbus2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_smbus2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus2_RANGES_NUM 0
#define DT_N_S_smbus2_FOREACH_RANGE(fn) 
#define DT_N_S_smbus2_IRQ_NUM 0
#define DT_N_S_smbus2_IRQ_LEVEL 0
#define DT_N_S_smbus2_COMPAT_MATCHES_st_stm32_smbus 1
#define DT_N_S_smbus2_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_smbus2_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_smbus2_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_smbus2_COMPAT_MODEL_IDX_0 "stm32-smbus"
#define DT_N_S_smbus2_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_smbus2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_smbus2_P_i2c DT_N_S_soc_S_i2c_40005800
#define DT_N_S_smbus2_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005800
#define DT_N_S_smbus2_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005800
#define DT_N_S_smbus2_P_i2c_IDX_0_EXISTS 1
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, i2c, 0)
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, i2c, 0)
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_i2c_LEN 1
#define DT_N_S_smbus2_P_i2c_EXISTS 1
#define DT_N_S_smbus2_P_status "disabled"
#define DT_N_S_smbus2_P_status_STRING_UNQUOTED disabled
#define DT_N_S_smbus2_P_status_STRING_TOKEN disabled
#define DT_N_S_smbus2_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_smbus2_P_status_IDX_0 "disabled"
#define DT_N_S_smbus2_P_status_IDX_0_EXISTS 1
#define DT_N_S_smbus2_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_smbus2_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus2_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, status, 0)
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, status, 0)
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, status, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, status, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_status_LEN 1
#define DT_N_S_smbus2_P_status_EXISTS 1
#define DT_N_S_smbus2_P_compatible {"st,stm32-smbus"}
#define DT_N_S_smbus2_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_smbus2_P_compatible_IDX_0 "st,stm32-smbus"
#define DT_N_S_smbus2_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus
#define DT_N_S_smbus2_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus
#define DT_N_S_smbus2_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, compatible, 0)
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, compatible, 0)
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus2_P_compatible_LEN 1
#define DT_N_S_smbus2_P_compatible_EXISTS 1
#define DT_N_S_smbus2_P_dma_coherent 0
#define DT_N_S_smbus2_P_dma_coherent_EXISTS 1
#define DT_N_S_smbus2_P_zephyr_deferred_init 0
#define DT_N_S_smbus2_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_smbus2_P_wakeup_source 0
#define DT_N_S_smbus2_P_wakeup_source_EXISTS 1
#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40007800
 *
 * Node identifier: DT_N_S_soc_S_i2c_40007800
 *
 * Binding (compatible = st,stm32-i2c-v2):
 *   $ZEPHYR_BASE/dts/bindings/i2c/st,stm32-i2c-v2.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40007800_PATH "/soc/i2c@40007800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40007800_FULL_NAME "i2c@40007800"
#define DT_N_S_soc_S_i2c_40007800_FULL_NAME_UNQUOTED i2c@40007800
#define DT_N_S_soc_S_i2c_40007800_FULL_NAME_TOKEN i2c_40007800
#define DT_N_S_soc_S_i2c_40007800_FULL_NAME_UPPER_TOKEN I2C_40007800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40007800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40007800_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_40007800_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2c_40007800_FOREACH_NODELABEL(fn) fn(i2c3)
#define DT_N_S_soc_S_i2c_40007800_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c3, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40007800_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40007800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40007800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_40007800_HASH GbbgBa6P3TV3qThPSZ3To0sobtbjrvg8BOI2phizbh4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40007800_ORD 25
#define DT_N_S_soc_S_i2c_40007800_ORD_STR_SORTABLE 00025

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40007800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40007800_SUPPORTS_ORDS \
	26, /* /smbus3 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40007800_EXISTS 1
#define DT_N_INST_2_st_stm32_i2c_v2 DT_N_S_soc_S_i2c_40007800
#define DT_N_NODELABEL_i2c3         DT_N_S_soc_S_i2c_40007800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40007800_REG_NUM 1
#define DT_N_S_soc_S_i2c_40007800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_REG_IDX_0_VAL_ADDRESS 1073772544 /* 0x40007800 */
#define DT_N_S_soc_S_i2c_40007800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_i2c_40007800_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_40007800, 0)
#define DT_N_S_soc_S_i2c_40007800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40007800, 0)
#define DT_N_S_soc_S_i2c_40007800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40007800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40007800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40007800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40007800_IRQ_NUM 2
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_VAL_irq 92
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_VAL_irq 93
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40007800_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_event_VAL_irq DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_event_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_event_VAL_priority DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_event_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_event_CONTROLLER DT_N_S_soc_S_i2c_40007800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_error_VAL_irq DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_error_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_error_VAL_priority DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_error_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_IRQ_NAME_error_CONTROLLER DT_N_S_soc_S_i2c_40007800_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_i2c_40007800_COMPAT_MATCHES_st_stm32_i2c_v2 1
#define DT_N_S_soc_S_i2c_40007800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_i2c_40007800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_COMPAT_MODEL_IDX_0 "stm32-i2c-v2"
#define DT_N_S_soc_S_i2c_40007800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40007800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40007800_P_reg {1073772544 /* 0x40007800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_i2c_40007800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_reg_IDX_0 1073772544
#define DT_N_S_soc_S_i2c_40007800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_i2c_40007800_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupts {92 /* 0x5c */, 0 /* 0x0 */, 93 /* 0x5d */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_0 92
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_2 93
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_i2c_40007800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_40007800_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_sq_size 4
#define DT_N_S_soc_S_i2c_40007800_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_cq_size 4
#define DT_N_S_soc_S_i2c_40007800_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_status "disabled"
#define DT_N_S_soc_S_i2c_40007800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2c_40007800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2c_40007800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2c_40007800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2c_40007800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2c_40007800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40007800, status, 0)
#define DT_N_S_soc_S_i2c_40007800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40007800, status, 0)
#define DT_N_S_soc_S_i2c_40007800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40007800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40007800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40007800_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_compatible {"st,stm32-i2c-v2"}
#define DT_N_S_soc_S_i2c_40007800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_compatible_IDX_0 "st,stm32-i2c-v2"
#define DT_N_S_soc_S_i2c_40007800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2
#define DT_N_S_soc_S_i2c_40007800_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2
#define DT_N_S_soc_S_i2c_40007800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2
#define DT_N_S_soc_S_i2c_40007800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40007800, compatible, 0)
#define DT_N_S_soc_S_i2c_40007800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40007800, compatible, 0)
#define DT_N_S_soc_S_i2c_40007800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40007800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40007800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40007800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names {"event", "error"}
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_0 "event"
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_0_STRING_UNQUOTED event
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_0_STRING_TOKEN event
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_1 "error"
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_1_STRING_UNQUOTED error
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_1_STRING_TOKEN error
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 0) \
	fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 1)
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40007800, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_i2c_40007800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_VAL_bits 1073741824
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_40007800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_i2c_40007800, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40007800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40007800, clocks, 0, bits)
#define DT_N_S_soc_S_i2c_40007800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_i2c_40007800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40007800, clocks, 0)
#define DT_N_S_soc_S_i2c_40007800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40007800, clocks, 0)
#define DT_N_S_soc_S_i2c_40007800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40007800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40007800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40007800_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_40007800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_dma_coherent 0
#define DT_N_S_soc_S_i2c_40007800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40007800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40007800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40007800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40007800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /smbus3
 *
 * Node identifier: DT_N_S_smbus3
 *
 * Binding (compatible = st,stm32-smbus):
 *   $ZEPHYR_BASE/dts/bindings/smbus/st,stm32-smbus.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_smbus3_PATH "/smbus3"

/* Node's name with unit-address: */
#define DT_N_S_smbus3_FULL_NAME "smbus3"
#define DT_N_S_smbus3_FULL_NAME_UNQUOTED smbus3
#define DT_N_S_smbus3_FULL_NAME_TOKEN smbus3
#define DT_N_S_smbus3_FULL_NAME_UPPER_TOKEN SMBUS3

/* Node parent (/) identifier: */
#define DT_N_S_smbus3_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_smbus3_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_smbus3_NODELABEL_NUM 1
#define DT_N_S_smbus3_FOREACH_NODELABEL(fn) fn(smbus3)
#define DT_N_S_smbus3_FOREACH_NODELABEL_VARGS(fn, ...) fn(smbus3, __VA_ARGS__)
#define DT_N_S_smbus3_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_smbus3_CHILD_NUM 0
#define DT_N_S_smbus3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_smbus3_FOREACH_CHILD(fn) 
#define DT_N_S_smbus3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_smbus3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_smbus3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_smbus3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_smbus3_HASH ZeVI1g__orT_bhXDEMbeNx9PIwW74xB8lEqisMROKVc

/* Node's dependency ordinal: */
#define DT_N_S_smbus3_ORD 26
#define DT_N_S_smbus3_ORD_STR_SORTABLE 00026

/* Ordinals for what this node depends on directly: */
#define DT_N_S_smbus3_REQUIRES_ORDS \
	0, /* / */ \
	25, /* /soc/i2c@40007800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_smbus3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_smbus3_EXISTS 1
#define DT_N_INST_2_st_stm32_smbus DT_N_S_smbus3
#define DT_N_NODELABEL_smbus3      DT_N_S_smbus3

/* Macros for properties that are special in the specification: */
#define DT_N_S_smbus3_REG_NUM 0
#define DT_N_S_smbus3_FOREACH_REG(fn) 
#define DT_N_S_smbus3_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_smbus3_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_smbus3_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_smbus3_RANGES_NUM 0
#define DT_N_S_smbus3_FOREACH_RANGE(fn) 
#define DT_N_S_smbus3_IRQ_NUM 0
#define DT_N_S_smbus3_IRQ_LEVEL 0
#define DT_N_S_smbus3_COMPAT_MATCHES_st_stm32_smbus 1
#define DT_N_S_smbus3_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_smbus3_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_smbus3_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_smbus3_COMPAT_MODEL_IDX_0 "stm32-smbus"
#define DT_N_S_smbus3_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_smbus3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_smbus3_P_i2c DT_N_S_soc_S_i2c_40007800
#define DT_N_S_smbus3_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40007800
#define DT_N_S_smbus3_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40007800
#define DT_N_S_smbus3_P_i2c_IDX_0_EXISTS 1
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, i2c, 0)
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, i2c, 0)
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_i2c_LEN 1
#define DT_N_S_smbus3_P_i2c_EXISTS 1
#define DT_N_S_smbus3_P_status "disabled"
#define DT_N_S_smbus3_P_status_STRING_UNQUOTED disabled
#define DT_N_S_smbus3_P_status_STRING_TOKEN disabled
#define DT_N_S_smbus3_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_smbus3_P_status_IDX_0 "disabled"
#define DT_N_S_smbus3_P_status_IDX_0_EXISTS 1
#define DT_N_S_smbus3_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_smbus3_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus3_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, status, 0)
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, status, 0)
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, status, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, status, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_status_LEN 1
#define DT_N_S_smbus3_P_status_EXISTS 1
#define DT_N_S_smbus3_P_compatible {"st,stm32-smbus"}
#define DT_N_S_smbus3_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_smbus3_P_compatible_IDX_0 "st,stm32-smbus"
#define DT_N_S_smbus3_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus
#define DT_N_S_smbus3_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus
#define DT_N_S_smbus3_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, compatible, 0)
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, compatible, 0)
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, compatible, 0, __VA_ARGS__)
#define DT_N_S_smbus3_P_compatible_LEN 1
#define DT_N_S_smbus3_P_compatible_EXISTS 1
#define DT_N_S_smbus3_P_dma_coherent 0
#define DT_N_S_smbus3_P_dma_coherent_EXISTS 1
#define DT_N_S_smbus3_P_zephyr_deferred_init 0
#define DT_N_S_smbus3_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_smbus3_P_wakeup_source 0
#define DT_N_S_smbus3_P_wakeup_source_EXISTS 1
#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /st-morpho-header
 *
 * Node identifier: DT_N_S_st_morpho_header
 *
 * Binding (compatible = st-morpho-header):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st-morpho-header.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_st_morpho_header_PATH "/st-morpho-header"

/* Node's name with unit-address: */
#define DT_N_S_st_morpho_header_FULL_NAME "st-morpho-header"
#define DT_N_S_st_morpho_header_FULL_NAME_UNQUOTED st-morpho-header
#define DT_N_S_st_morpho_header_FULL_NAME_TOKEN st_morpho_header
#define DT_N_S_st_morpho_header_FULL_NAME_UPPER_TOKEN ST_MORPHO_HEADER

/* Node parent (/) identifier: */
#define DT_N_S_st_morpho_header_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_st_morpho_header_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_st_morpho_header_NODELABEL_NUM 1
#define DT_N_S_st_morpho_header_FOREACH_NODELABEL(fn) fn(st_morpho_header)
#define DT_N_S_st_morpho_header_FOREACH_NODELABEL_VARGS(fn, ...) fn(st_morpho_header, __VA_ARGS__)
#define DT_N_S_st_morpho_header_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_st_morpho_header_CHILD_NUM 0
#define DT_N_S_st_morpho_header_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_st_morpho_header_FOREACH_CHILD(fn) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_st_morpho_header_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_st_morpho_header_HASH C6Ew8HpPaWbuNGwIwt5R8f6EkxnSDJUUmS562ynELt8

/* Node's dependency ordinal: */
#define DT_N_S_st_morpho_header_ORD 27
#define DT_N_S_st_morpho_header_ORD_STR_SORTABLE 00027

/* Ordinals for what this node depends on directly: */
#define DT_N_S_st_morpho_header_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_st_morpho_header_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_st_morpho_header_EXISTS 1
#define DT_N_INST_0_st_morpho_header    DT_N_S_st_morpho_header
#define DT_N_NODELABEL_st_morpho_header DT_N_S_st_morpho_header

/* Macros for properties that are special in the specification: */
#define DT_N_S_st_morpho_header_REG_NUM 0
#define DT_N_S_st_morpho_header_FOREACH_REG(fn) 
#define DT_N_S_st_morpho_header_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_st_morpho_header_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_st_morpho_header_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_st_morpho_header_RANGES_NUM 0
#define DT_N_S_st_morpho_header_FOREACH_RANGE(fn) 
#define DT_N_S_st_morpho_header_IRQ_NUM 0
#define DT_N_S_st_morpho_header_IRQ_LEVEL 0
#define DT_N_S_st_morpho_header_COMPAT_MATCHES_st_morpho_header 1
#define DT_N_S_st_morpho_header_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_st_morpho_header_PINCTRL_NUM 0

/* Map properties: */
#define DT_N_S_st_morpho_header_P_gpio_map_LEN 51
#define DT_N_S_st_morpho_header_P_gpio_map_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0 10
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0 11
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0 12
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0 3
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0 12
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0 13
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0 14
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0 14
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0 16
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0 15
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0 20
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0 22
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0 13
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0 24
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0 14
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0 26
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0 15
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_0 27
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_11_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_0 28
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_12_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_0 29
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_13_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_0 30
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_14_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_0 31
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_15_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_0 33
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_16_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_0 34
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_0 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_17_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_0 35
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_18_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_0 36
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_19_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_0 37
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_20_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_0 72
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_21_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_CHILD_SPECIFIER_IDX_0 73
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_22_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_CHILD_SPECIFIER_IDX_0 74
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_23_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_CHILD_SPECIFIER_IDX_0 75
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_24_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_CHILD_SPECIFIER_IDX_0 76
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_25_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_CHILD_SPECIFIER_IDX_0 77
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_26_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_CHILD_SPECIFIER_IDX_0 82
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT_SPECIFIER_IDX_0 13
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_27_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_CHILD_SPECIFIER_IDX_0 83
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT_SPECIFIER_IDX_0 12
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_28_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_CHILD_SPECIFIER_IDX_0 84
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT_SPECIFIER_IDX_0 14
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_29_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_CHILD_SPECIFIER_IDX_0 85
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT_SPECIFIER_IDX_0 11
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_30_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_CHILD_SPECIFIER_IDX_0 86
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT_SPECIFIER_IDX_0 15
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_31_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_CHILD_SPECIFIER_IDX_0 87
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT_SPECIFIER_IDX_0 12
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_32_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_CHILD_SPECIFIER_IDX_0 88
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_33_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_CHILD_SPECIFIER_IDX_0 89
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT_SPECIFIER_IDX_0 11
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_34_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_CHILD_SPECIFIER_IDX_0 90
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_35_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_CHILD_SPECIFIER_IDX_0 92
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_36_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_CHILD_SPECIFIER_IDX_0 93
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT_SPECIFIER_IDX_0 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_37_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_CHILD_SPECIFIER_IDX_0 94
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_38_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_CHILD_SPECIFIER_IDX_0 95
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_39_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_CHILD_SPECIFIER_IDX_0 96
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT_SPECIFIER_IDX_0 10
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_40_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_CHILD_SPECIFIER_IDX_0 97
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_41_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_CHILD_SPECIFIER_IDX_0 98
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_42_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_CHILD_SPECIFIER_IDX_0 99
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_43_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_CHILD_SPECIFIER_IDX_0 100
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_44_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_CHILD_SPECIFIER_IDX_0 101
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_45_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_CHILD_SPECIFIER_IDX_0 102
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_46_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_CHILD_SPECIFIER_IDX_0 104
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT_SPECIFIER_IDX_0 10
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_47_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_CHILD_SPECIFIER_IDX_0 105
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_48_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_CHILD_SPECIFIER_IDX_0 106
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT_SPECIFIER_IDX_0 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_49_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_CHILD_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_CHILD_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_CHILD_SPECIFIER_IDX_0 108
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT_ADDRESS_LEN 0
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT_SPECIFIER_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_MAP_ENTRY_50_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_FOREACH_MAP_ENTRY(fn) fn(DT_N_S_st_morpho_header, gpio_map, 0) \
	fn(DT_N_S_st_morpho_header, gpio_map, 1) \
	fn(DT_N_S_st_morpho_header, gpio_map, 2) \
	fn(DT_N_S_st_morpho_header, gpio_map, 3) \
	fn(DT_N_S_st_morpho_header, gpio_map, 4) \
	fn(DT_N_S_st_morpho_header, gpio_map, 5) \
	fn(DT_N_S_st_morpho_header, gpio_map, 6) \
	fn(DT_N_S_st_morpho_header, gpio_map, 7) \
	fn(DT_N_S_st_morpho_header, gpio_map, 8) \
	fn(DT_N_S_st_morpho_header, gpio_map, 9) \
	fn(DT_N_S_st_morpho_header, gpio_map, 10) \
	fn(DT_N_S_st_morpho_header, gpio_map, 11) \
	fn(DT_N_S_st_morpho_header, gpio_map, 12) \
	fn(DT_N_S_st_morpho_header, gpio_map, 13) \
	fn(DT_N_S_st_morpho_header, gpio_map, 14) \
	fn(DT_N_S_st_morpho_header, gpio_map, 15) \
	fn(DT_N_S_st_morpho_header, gpio_map, 16) \
	fn(DT_N_S_st_morpho_header, gpio_map, 17) \
	fn(DT_N_S_st_morpho_header, gpio_map, 18) \
	fn(DT_N_S_st_morpho_header, gpio_map, 19) \
	fn(DT_N_S_st_morpho_header, gpio_map, 20) \
	fn(DT_N_S_st_morpho_header, gpio_map, 21) \
	fn(DT_N_S_st_morpho_header, gpio_map, 22) \
	fn(DT_N_S_st_morpho_header, gpio_map, 23) \
	fn(DT_N_S_st_morpho_header, gpio_map, 24) \
	fn(DT_N_S_st_morpho_header, gpio_map, 25) \
	fn(DT_N_S_st_morpho_header, gpio_map, 26) \
	fn(DT_N_S_st_morpho_header, gpio_map, 27) \
	fn(DT_N_S_st_morpho_header, gpio_map, 28) \
	fn(DT_N_S_st_morpho_header, gpio_map, 29) \
	fn(DT_N_S_st_morpho_header, gpio_map, 30) \
	fn(DT_N_S_st_morpho_header, gpio_map, 31) \
	fn(DT_N_S_st_morpho_header, gpio_map, 32) \
	fn(DT_N_S_st_morpho_header, gpio_map, 33) \
	fn(DT_N_S_st_morpho_header, gpio_map, 34) \
	fn(DT_N_S_st_morpho_header, gpio_map, 35) \
	fn(DT_N_S_st_morpho_header, gpio_map, 36) \
	fn(DT_N_S_st_morpho_header, gpio_map, 37) \
	fn(DT_N_S_st_morpho_header, gpio_map, 38) \
	fn(DT_N_S_st_morpho_header, gpio_map, 39) \
	fn(DT_N_S_st_morpho_header, gpio_map, 40) \
	fn(DT_N_S_st_morpho_header, gpio_map, 41) \
	fn(DT_N_S_st_morpho_header, gpio_map, 42) \
	fn(DT_N_S_st_morpho_header, gpio_map, 43) \
	fn(DT_N_S_st_morpho_header, gpio_map, 44) \
	fn(DT_N_S_st_morpho_header, gpio_map, 45) \
	fn(DT_N_S_st_morpho_header, gpio_map, 46) \
	fn(DT_N_S_st_morpho_header, gpio_map, 47) \
	fn(DT_N_S_st_morpho_header, gpio_map, 48) \
	fn(DT_N_S_st_morpho_header, gpio_map, 49) \
	fn(DT_N_S_st_morpho_header, gpio_map, 50)
#define DT_N_S_st_morpho_header_P_gpio_map_FOREACH_MAP_ENTRY_SEP(fn, sep) fn(DT_N_S_st_morpho_header, gpio_map, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 21) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 22) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 23) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 24) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 25) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 26) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 27) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 28) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 29) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 30) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 31) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 32) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 33) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 34) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 35) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 36) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 37) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 38) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 39) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 40) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 41) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 42) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 43) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 44) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 45) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 46) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 47) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 48) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 49) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 50)
#define DT_N_S_st_morpho_header_P_gpio_map_FOREACH_MAP_ENTRY_VARGS(fn, ...) fn(DT_N_S_st_morpho_header, gpio_map, 0, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 1, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 2, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 3, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 4, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 5, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 6, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 7, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 8, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 9, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 10, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 11, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 12, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 13, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 14, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 15, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 16, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 17, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 18, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 19, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 20, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 21, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 22, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 23, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 24, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 25, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 26, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 27, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 28, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 29, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 30, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 31, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 32, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 33, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 34, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 35, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 36, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 37, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 38, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 39, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 40, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 41, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 42, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 43, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 44, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 45, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 46, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 47, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 48, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 49, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map, 50, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_gpio_map_FOREACH_MAP_ENTRY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_st_morpho_header, gpio_map, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map, 50, __VA_ARGS__)

/* Generic property macros: */
#define DT_N_S_st_morpho_header_P_gpio_map_mask {255 /* 0xff */, 0 /* 0x0 */}
#define DT_N_S_st_morpho_header_P_gpio_map_mask_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_mask_IDX_0 255
#define DT_N_S_st_morpho_header_P_gpio_map_mask_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_mask_IDX_1 0
#define DT_N_S_st_morpho_header_P_gpio_map_mask_FOREACH_PROP_ELEM(fn) fn(DT_N_S_st_morpho_header, gpio_map_mask, 0) \
	fn(DT_N_S_st_morpho_header, gpio_map_mask, 1)
#define DT_N_S_st_morpho_header_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_st_morpho_header, gpio_map_mask, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map_mask, 1)
#define DT_N_S_st_morpho_header_P_gpio_map_mask_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_st_morpho_header, gpio_map_mask, 0, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_st_morpho_header, gpio_map_mask, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_gpio_map_mask_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_mask_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru {0 /* 0x0 */, 127 /* 0x7f */}
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_IDX_0 0
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_IDX_1_EXISTS 1
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_IDX_1 127
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_FOREACH_PROP_ELEM(fn) fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 0) \
	fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 1)
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 1)
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 0, __VA_ARGS__) \
	fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_st_morpho_header, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_LEN 2
#define DT_N_S_st_morpho_header_P_gpio_map_pass_thru_EXISTS 1
#define DT_N_S_st_morpho_header_P_compatible {"st-morpho-header"}
#define DT_N_S_st_morpho_header_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_st_morpho_header_P_compatible_IDX_0 "st-morpho-header"
#define DT_N_S_st_morpho_header_P_compatible_IDX_0_STRING_UNQUOTED st-morpho-header
#define DT_N_S_st_morpho_header_P_compatible_IDX_0_STRING_TOKEN st_morpho_header
#define DT_N_S_st_morpho_header_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_MORPHO_HEADER
#define DT_N_S_st_morpho_header_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_st_morpho_header, compatible, 0)
#define DT_N_S_st_morpho_header_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_st_morpho_header, compatible, 0)
#define DT_N_S_st_morpho_header_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_st_morpho_header, compatible, 0, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_st_morpho_header, compatible, 0, __VA_ARGS__)
#define DT_N_S_st_morpho_header_P_compatible_LEN 1
#define DT_N_S_st_morpho_header_P_compatible_EXISTS 1
#define DT_N_S_st_morpho_header_P_dma_coherent 0
#define DT_N_S_st_morpho_header_P_dma_coherent_EXISTS 1
#define DT_N_S_st_morpho_header_P_zephyr_deferred_init 0
#define DT_N_S_st_morpho_header_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_st_morpho_header_P_wakeup_source 0
#define DT_N_S_st_morpho_header_P_wakeup_source_EXISTS 1
#define DT_N_S_st_morpho_header_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_st_morpho_header_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /vbat
 *
 * Node identifier: DT_N_S_vbat
 *
 * Binding (compatible = st,stm32-vbat):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-vbat.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_vbat_PATH "/vbat"

/* Node's name with unit-address: */
#define DT_N_S_vbat_FULL_NAME "vbat"
#define DT_N_S_vbat_FULL_NAME_UNQUOTED vbat
#define DT_N_S_vbat_FULL_NAME_TOKEN vbat
#define DT_N_S_vbat_FULL_NAME_UPPER_TOKEN VBAT

/* Node parent (/) identifier: */
#define DT_N_S_vbat_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_vbat_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_vbat_NODELABEL_NUM 1
#define DT_N_S_vbat_FOREACH_NODELABEL(fn) fn(vbat)
#define DT_N_S_vbat_FOREACH_NODELABEL_VARGS(fn, ...) fn(vbat, __VA_ARGS__)
#define DT_N_S_vbat_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_vbat_CHILD_NUM 0
#define DT_N_S_vbat_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_vbat_FOREACH_CHILD(fn) 
#define DT_N_S_vbat_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_vbat_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_vbat_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_vbat_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_vbat_HASH 6jTjjWCiokAcWwHDg9DIiUBaK7_R_tkCJ6unpENFBIY

/* Node's dependency ordinal: */
#define DT_N_S_vbat_ORD 28
#define DT_N_S_vbat_ORD_STR_SORTABLE 00028

/* Ordinals for what this node depends on directly: */
#define DT_N_S_vbat_REQUIRES_ORDS \
	0, /* / */ \
	10, /* /soc/adc@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_vbat_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_vbat_EXISTS 1
#define DT_N_INST_0_st_stm32_vbat DT_N_S_vbat
#define DT_N_NODELABEL_vbat       DT_N_S_vbat

/* Macros for properties that are special in the specification: */
#define DT_N_S_vbat_REG_NUM 0
#define DT_N_S_vbat_FOREACH_REG(fn) 
#define DT_N_S_vbat_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_vbat_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_vbat_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vbat_RANGES_NUM 0
#define DT_N_S_vbat_FOREACH_RANGE(fn) 
#define DT_N_S_vbat_IRQ_NUM 0
#define DT_N_S_vbat_IRQ_LEVEL 0
#define DT_N_S_vbat_COMPAT_MATCHES_st_stm32_vbat 1
#define DT_N_S_vbat_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_vbat_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_vbat_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_vbat_COMPAT_MODEL_IDX_0 "stm32-vbat"
#define DT_N_S_vbat_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_vbat_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_vbat_P_io_channels_IDX_0_EXISTS 1
#define DT_N_S_vbat_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_50000000
#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input 17
#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input_EXISTS 1
#define DT_N_S_vbat_P_io_channels_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_vbat, io_channels, 0, input)
#define DT_N_S_vbat_P_io_channels_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_vbat, io_channels, 0, input)
#define DT_N_S_vbat_P_io_channels_IDX_0_NUM_CELLS 1
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, io_channels, 0)
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, io_channels, 0)
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_io_channels_LEN 1
#define DT_N_S_vbat_P_io_channels_EXISTS 1
#define DT_N_S_vbat_P_ratio 3
#define DT_N_S_vbat_P_ratio_EXISTS 1
#define DT_N_S_vbat_P_status "disabled"
#define DT_N_S_vbat_P_status_STRING_UNQUOTED disabled
#define DT_N_S_vbat_P_status_STRING_TOKEN disabled
#define DT_N_S_vbat_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_vbat_P_status_IDX_0 "disabled"
#define DT_N_S_vbat_P_status_IDX_0_EXISTS 1
#define DT_N_S_vbat_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_vbat_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_vbat_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, status, 0)
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, status, 0)
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, status, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, status, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_status_LEN 1
#define DT_N_S_vbat_P_status_EXISTS 1
#define DT_N_S_vbat_P_compatible {"st,stm32-vbat"}
#define DT_N_S_vbat_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_vbat_P_compatible_IDX_0 "st,stm32-vbat"
#define DT_N_S_vbat_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-vbat
#define DT_N_S_vbat_P_compatible_IDX_0_STRING_TOKEN st_stm32_vbat
#define DT_N_S_vbat_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_VBAT
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, compatible, 0)
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, compatible, 0)
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, compatible, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, compatible, 0, __VA_ARGS__)
#define DT_N_S_vbat_P_compatible_LEN 1
#define DT_N_S_vbat_P_compatible_EXISTS 1
#define DT_N_S_vbat_P_dma_coherent 0
#define DT_N_S_vbat_P_dma_coherent_EXISTS 1
#define DT_N_S_vbat_P_zephyr_deferred_init 0
#define DT_N_S_vbat_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_vbat_P_wakeup_source 0
#define DT_N_S_vbat_P_wakeup_source_EXISTS 1
#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/vrefint@aa
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_PATH "/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/vrefint@aa"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FULL_NAME "vrefint@aa"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FULL_NAME_UNQUOTED vrefint@aa
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FULL_NAME_TOKEN vrefint_aa
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FULL_NAME_UPPER_TOKEN VREFINT_AA

/* Node parent (/soc/flash-controller@40022000/flash@1fff7500/nvmem-layout) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_NODELABEL(fn) fn(vrefint_otp)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_NODELABEL_VARGS(fn, ...) fn(vrefint_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_HASH 15kzbjjp0xPhu39T9qirILipraivWl7Fqkx42ZFtMwU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_ORD 29
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_ORD_STR_SORTABLE 00029

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_REQUIRES_ORDS \
	13, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_SUPPORTS_ORDS \
	30, /* /vref */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_EXISTS 1
#define DT_N_NODELABEL_vrefint_otp DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_REG_IDX_0_VAL_ADDRESS 170 /* 0xaa */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_REG_IDX_0_VAL_SIZE 2 /* 0x2 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_reg {170 /* 0xaa */, 2 /* 0x2 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_reg_IDX_0 170
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_reg_IDX_1 2
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_read_only 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa_P_read_only_EXISTS 1

/*
 * Devicetree node: /vref
 *
 * Node identifier: DT_N_S_vref
 *
 * Binding (compatible = st,stm32-vref):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-vref.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_vref_PATH "/vref"

/* Node's name with unit-address: */
#define DT_N_S_vref_FULL_NAME "vref"
#define DT_N_S_vref_FULL_NAME_UNQUOTED vref
#define DT_N_S_vref_FULL_NAME_TOKEN vref
#define DT_N_S_vref_FULL_NAME_UPPER_TOKEN VREF

/* Node parent (/) identifier: */
#define DT_N_S_vref_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_vref_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_vref_NODELABEL_NUM 1
#define DT_N_S_vref_FOREACH_NODELABEL(fn) fn(vref)
#define DT_N_S_vref_FOREACH_NODELABEL_VARGS(fn, ...) fn(vref, __VA_ARGS__)
#define DT_N_S_vref_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_vref_CHILD_NUM 0
#define DT_N_S_vref_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_vref_FOREACH_CHILD(fn) 
#define DT_N_S_vref_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_vref_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_vref_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_vref_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_vref_HASH _KQ_hQT8vlL_HGgSo8B0PN_M_dmG5lMZ2C1aGmWYFog

/* Node's dependency ordinal: */
#define DT_N_S_vref_ORD 30
#define DT_N_S_vref_ORD_STR_SORTABLE 00030

/* Ordinals for what this node depends on directly: */
#define DT_N_S_vref_REQUIRES_ORDS \
	0, /* / */ \
	10, /* /soc/adc@50000000 */ \
	29, /* /soc/flash-controller@40022000/flash@1fff7500/nvmem-layout/vrefint@aa */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_vref_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_vref_EXISTS 1
#define DT_N_INST_0_st_stm32_vref DT_N_S_vref
#define DT_N_NODELABEL_vref       DT_N_S_vref

/* Macros for properties that are special in the specification: */
#define DT_N_S_vref_REG_NUM 0
#define DT_N_S_vref_FOREACH_REG(fn) 
#define DT_N_S_vref_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_vref_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_vref_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_vref_RANGES_NUM 0
#define DT_N_S_vref_FOREACH_RANGE(fn) 
#define DT_N_S_vref_IRQ_NUM 0
#define DT_N_S_vref_IRQ_LEVEL 0
#define DT_N_S_vref_COMPAT_MATCHES_st_stm32_vref 1
#define DT_N_S_vref_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_vref_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_vref_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_vref_COMPAT_MODEL_IDX_0 "stm32-vref"
#define DT_N_S_vref_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_vref_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_vref_P_nvmem_cells_IDX_0_EXISTS 1
#define DT_N_S_vref_P_nvmem_cells_IDX_0_PH DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa
#define DT_N_S_vref_P_nvmem_cells_IDX_0_FOREACH_CELL(fn) 
#define DT_N_S_vref_P_nvmem_cells_IDX_0_FOREACH_CELL_SEP(fn, sep) 
#define DT_N_S_vref_P_nvmem_cells_IDX_0_NUM_CELLS 0
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, nvmem_cells, 0)
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, nvmem_cells, 0)
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, nvmem_cells, 0, __VA_ARGS__)
#define DT_N_S_vref_P_nvmem_cells_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, nvmem_cells, 0, __VA_ARGS__)
#define DT_N_S_vref_P_nvmem_cells_LEN 1
#define DT_N_S_vref_P_nvmem_cells_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_mv 3000
#define DT_N_S_vref_P_vrefint_cal_mv_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution 12
#define DT_N_S_vref_P_vrefint_cal_resolution_IDX_0_ENUM_IDX 0
#define DT_N_S_vref_P_vrefint_cal_resolution_IDX_0_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution_IDX_0_ENUM_VAL_12_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution_ENUM_VAL_12_EXISTS 1
#define DT_N_S_vref_P_vrefint_cal_resolution_EXISTS 1
#define DT_N_S_vref_P_status "disabled"
#define DT_N_S_vref_P_status_STRING_UNQUOTED disabled
#define DT_N_S_vref_P_status_STRING_TOKEN disabled
#define DT_N_S_vref_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_vref_P_status_IDX_0 "disabled"
#define DT_N_S_vref_P_status_IDX_0_EXISTS 1
#define DT_N_S_vref_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_vref_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_vref_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, status, 0)
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, status, 0)
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, status, 0, __VA_ARGS__)
#define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, status, 0, __VA_ARGS__)
#define DT_N_S_vref_P_status_LEN 1
#define DT_N_S_vref_P_status_EXISTS 1
#define DT_N_S_vref_P_compatible {"st,stm32-vref"}
#define DT_N_S_vref_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_vref_P_compatible_IDX_0 "st,stm32-vref"
#define DT_N_S_vref_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-vref
#define DT_N_S_vref_P_compatible_IDX_0_STRING_TOKEN st_stm32_vref
#define DT_N_S_vref_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_VREF
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, compatible, 0)
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, compatible, 0)
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, compatible, 0, __VA_ARGS__)
#define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, compatible, 0, __VA_ARGS__)
#define DT_N_S_vref_P_compatible_LEN 1
#define DT_N_S_vref_P_compatible_EXISTS 1
#define DT_N_S_vref_P_dma_coherent 0
#define DT_N_S_vref_P_dma_coherent_EXISTS 1
#define DT_N_S_vref_P_io_channels_IDX_0_EXISTS 1
#define DT_N_S_vref_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_50000000
#define DT_N_S_vref_P_io_channels_IDX_0_VAL_input 18
#define DT_N_S_vref_P_io_channels_IDX_0_VAL_input_EXISTS 1
#define DT_N_S_vref_P_io_channels_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_vref, io_channels, 0, input)
#define DT_N_S_vref_P_io_channels_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_vref, io_channels, 0, input)
#define DT_N_S_vref_P_io_channels_IDX_0_NUM_CELLS 1
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, io_channels, 0)
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, io_channels, 0)
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vref_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vref, io_channels, 0, __VA_ARGS__)
#define DT_N_S_vref_P_io_channels_LEN 1
#define DT_N_S_vref_P_io_channels_EXISTS 1
#define DT_N_S_vref_P_zephyr_deferred_init 0
#define DT_N_S_vref_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_vref_P_wakeup_source 0
#define DT_N_S_vref_P_wakeup_source_EXISTS 1
#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-hsi
 *
 * Node identifier: DT_N_S_clocks_S_clk_hsi
 *
 * Binding (compatible = fixed-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/fixed-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_hsi_PATH "/clocks/clk-hsi"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME "clk-hsi"
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_UNQUOTED clk-hsi
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_TOKEN clk_hsi
#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_UPPER_TOKEN CLK_HSI

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_hsi_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_hsi_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_hsi_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_hsi_FOREACH_NODELABEL(fn) fn(clk_hsi)
#define DT_N_S_clocks_S_clk_hsi_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_hsi, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_hsi_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_hsi_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_hsi_HASH kE6dGnI__HuixEc_o2mPIojHDSoRqqYmExJJycW6WDM

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_hsi_ORD 31
#define DT_N_S_clocks_S_clk_hsi_ORD_STR_SORTABLE 00031

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_hsi_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_hsi_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_hsi_EXISTS 1
#define DT_N_INST_2_fixed_clock DT_N_S_clocks_S_clk_hsi
#define DT_N_NODELABEL_clk_hsi  DT_N_S_clocks_S_clk_hsi

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_hsi_REG_NUM 0
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hsi_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_hsi_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_hsi_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_hsi_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_hsi_COMPAT_MATCHES_fixed_clock 1
#define DT_N_S_clocks_S_clk_hsi_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_hsi_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_hsi_P_clock_frequency 16000000
#define DT_N_S_clocks_S_clk_hsi_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status "disabled"
#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_UNQUOTED disabled
#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_TOKEN disabled
#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0 "disabled"
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi, status, 0)
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi, status, 0)
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_status_LEN 1
#define DT_N_S_clocks_S_clk_hsi_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_compatible {"fixed-clock"}
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0 "fixed-clock"
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_TOKEN fixed_clock
#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_hsi_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_hsi_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_hsi_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_hsi_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-hsi48
 *
 * Node identifier: DT_N_S_clocks_S_clk_hsi48
 *
 * Binding (compatible = fixed-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/fixed-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_hsi48_PATH "/clocks/clk-hsi48"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME "clk-hsi48"
#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME_UNQUOTED clk-hsi48
#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME_TOKEN clk_hsi48
#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME_UPPER_TOKEN CLK_HSI48

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_hsi48_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_hsi48_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_hsi48_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_NODELABEL(fn) fn(clk_hsi48)
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_hsi48, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_hsi48_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_hsi48_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_hsi48_HASH m4q2NUiXYm_f1RVl9VGtz8iGJxJSrtVw_lCXFQUVjsw

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_hsi48_ORD 32
#define DT_N_S_clocks_S_clk_hsi48_ORD_STR_SORTABLE 00032

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_hsi48_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_hsi48_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_hsi48_EXISTS 1
#define DT_N_INST_0_fixed_clock  DT_N_S_clocks_S_clk_hsi48
#define DT_N_NODELABEL_clk_hsi48 DT_N_S_clocks_S_clk_hsi48

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_hsi48_REG_NUM 0
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_hsi48_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_hsi48_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_hsi48_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_hsi48_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_hsi48_COMPAT_MATCHES_fixed_clock 1
#define DT_N_S_clocks_S_clk_hsi48_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_hsi48_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_hsi48_P_clock_frequency 48000000
#define DT_N_S_clocks_S_clk_hsi48_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_status "okay"
#define DT_N_S_clocks_S_clk_hsi48_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_clk_hsi48_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_clk_hsi48_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi48, status, 0)
#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi48, status, 0)
#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi48, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi48, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi48_P_status_LEN 1
#define DT_N_S_clocks_S_clk_hsi48_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_compatible {"fixed-clock"}
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0 "fixed-clock"
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_STRING_TOKEN fixed_clock
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0)
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0)
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_hsi48_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_hsi48_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_hsi48_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-lse
 *
 * Node identifier: DT_N_S_clocks_S_clk_lse
 *
 * Binding (compatible = st,stm32-lse-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/st,stm32-lse-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_lse_PATH "/clocks/clk-lse"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_lse_FULL_NAME "clk-lse"
#define DT_N_S_clocks_S_clk_lse_FULL_NAME_UNQUOTED clk-lse
#define DT_N_S_clocks_S_clk_lse_FULL_NAME_TOKEN clk_lse
#define DT_N_S_clocks_S_clk_lse_FULL_NAME_UPPER_TOKEN CLK_LSE

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_lse_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_lse_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_lse_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_lse_FOREACH_NODELABEL(fn) fn(clk_lse)
#define DT_N_S_clocks_S_clk_lse_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_lse, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_lse_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_lse_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_lse_HASH RRqOX2XdydrKvwOwHO0Kh3mPfPtUsDJrDySCwF316Ek

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_lse_ORD 33
#define DT_N_S_clocks_S_clk_lse_ORD_STR_SORTABLE 00033

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_lse_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_lse_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_lse_EXISTS 1
#define DT_N_INST_0_st_stm32_lse_clock DT_N_S_clocks_S_clk_lse
#define DT_N_NODELABEL_clk_lse         DT_N_S_clocks_S_clk_lse

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_lse_REG_NUM 0
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lse_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lse_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_lse_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_lse_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_lse_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_lse_COMPAT_MATCHES_st_stm32_lse_clock 1
#define DT_N_S_clocks_S_clk_lse_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_clocks_S_clk_lse_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_COMPAT_MODEL_IDX_0 "stm32-lse-clock"
#define DT_N_S_clocks_S_clk_lse_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_lse_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_lse_P_driving_capability 0
#define DT_N_S_clocks_S_clk_lse_P_driving_capability_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_lse_P_driving_capability_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_driving_capability_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_driving_capability_ENUM_VAL_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_driving_capability_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_lse_bypass 0
#define DT_N_S_clocks_S_clk_lse_P_lse_bypass_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_clock_frequency 32768
#define DT_N_S_clocks_S_clk_lse_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status "okay"
#define DT_N_S_clocks_S_clk_lse_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_clk_lse_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_clk_lse_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lse, status, 0)
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lse, status, 0)
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lse, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_status_LEN 1
#define DT_N_S_clocks_S_clk_lse_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_compatible {"st,stm32-lse-clock"}
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0 "st,stm32-lse-clock"
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lse-clock
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_TOKEN st_stm32_lse_clock
#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LSE_CLOCK
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lse, compatible, 0)
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lse, compatible, 0)
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lse, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lse_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_lse_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_lse_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_lse_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_lse_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_lse_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_lse_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /clocks/clk-lsi
 *
 * Node identifier: DT_N_S_clocks_S_clk_lsi
 *
 * Binding (compatible = fixed-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/fixed-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clocks_S_clk_lsi_PATH "/clocks/clk-lsi"

/* Node's name with unit-address: */
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME "clk-lsi"
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_UNQUOTED clk-lsi
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_TOKEN clk_lsi
#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_UPPER_TOKEN CLK_LSI

/* Node parent (/clocks) identifier: */
#define DT_N_S_clocks_S_clk_lsi_PARENT DT_N_S_clocks

/* Node's index in its parent's list of children: */
#define DT_N_S_clocks_S_clk_lsi_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_clocks_S_clk_lsi_NODELABEL_NUM 1
#define DT_N_S_clocks_S_clk_lsi_FOREACH_NODELABEL(fn) fn(clk_lsi)
#define DT_N_S_clocks_S_clk_lsi_FOREACH_NODELABEL_VARGS(fn, ...) fn(clk_lsi, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_FOREACH_ANCESTOR(fn) fn(DT_N_S_clocks) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clocks_S_clk_lsi_CHILD_NUM 0
#define DT_N_S_clocks_S_clk_lsi_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD(fn) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clocks_S_clk_lsi_HASH y39tlAqwOoFHfznEDn2ZnvWSfYGNtJJvOJBnTUmFguY

/* Node's dependency ordinal: */
#define DT_N_S_clocks_S_clk_lsi_ORD 34
#define DT_N_S_clocks_S_clk_lsi_ORD_STR_SORTABLE 00034

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clocks_S_clk_lsi_REQUIRES_ORDS \
	6, /* /clocks */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clocks_S_clk_lsi_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_clocks_S_clk_lsi_EXISTS 1
#define DT_N_INST_1_fixed_clock DT_N_S_clocks_S_clk_lsi
#define DT_N_NODELABEL_clk_lsi  DT_N_S_clocks_S_clk_lsi

/* Macros for properties that are special in the specification: */
#define DT_N_S_clocks_S_clk_lsi_REG_NUM 0
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG(fn) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clocks_S_clk_lsi_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clocks_S_clk_lsi_RANGES_NUM 0
#define DT_N_S_clocks_S_clk_lsi_FOREACH_RANGE(fn) 
#define DT_N_S_clocks_S_clk_lsi_IRQ_NUM 0
#define DT_N_S_clocks_S_clk_lsi_IRQ_LEVEL 0
#define DT_N_S_clocks_S_clk_lsi_COMPAT_MATCHES_fixed_clock 1
#define DT_N_S_clocks_S_clk_lsi_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clocks_S_clk_lsi_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clocks_S_clk_lsi_P_clock_frequency 32000
#define DT_N_S_clocks_S_clk_lsi_P_clock_frequency_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status "okay"
#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_UNQUOTED okay
#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_TOKEN okay
#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0 "okay"
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lsi, status, 0)
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lsi, status, 0)
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lsi, status, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_status_LEN 1
#define DT_N_S_clocks_S_clk_lsi_P_status_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_compatible {"fixed-clock"}
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0 "fixed-clock"
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_TOKEN fixed_clock
#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0, __VA_ARGS__)
#define DT_N_S_clocks_S_clk_lsi_P_compatible_LEN 1
#define DT_N_S_clocks_S_clk_lsi_P_compatible_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_dma_coherent 0
#define DT_N_S_clocks_S_clk_lsi_P_dma_coherent_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_deferred_init 0
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_wakeup_source 0
#define DT_N_S_clocks_S_clk_lsi_P_wakeup_source_EXISTS 1
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_clocks_S_clk_lsi_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"
#define DT_N_S_cpus_FULL_NAME_UNQUOTED cpus
#define DT_N_S_cpus_FULL_NAME_TOKEN cpus
#define DT_N_S_cpus_FULL_NAME_UPPER_TOKEN CPUS

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_NODELABEL_NUM 0
#define DT_N_S_cpus_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_cpus_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_CHILD_NUM 2
#define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_cpus_CHILD_UNIT_ADDR_INT_0 DT_N_S_cpus_S_cpu_0
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_cpus_HASH iL3XRGZVvvtpNJqKV0_jvtuXF7m6kgky4nI2ifizwdg

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 35
#define DT_N_S_cpus_ORD_STR_SORTABLE 00035

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	36, /* /cpus/power-states */ \
	39, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_FOREACH_REG(fn) 
#define DT_N_S_cpus_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_IRQ_LEVEL 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/power-states
 *
 * Node identifier: DT_N_S_cpus_S_power_states
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_PATH "/cpus/power-states"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_FULL_NAME "power-states"
#define DT_N_S_cpus_S_power_states_FULL_NAME_UNQUOTED power-states
#define DT_N_S_cpus_S_power_states_FULL_NAME_TOKEN power_states
#define DT_N_S_cpus_S_power_states_FULL_NAME_UPPER_TOKEN POWER_STATES

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_power_states_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_NODELABEL_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_S_power_states_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_CHILD_NUM 2
#define DT_N_S_cpus_S_power_states_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_power_states_S_state0) fn(DT_N_S_cpus_S_power_states_S_state1)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_state0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states_S_state1)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_power_states_S_state0) fn(DT_N_S_cpus_S_power_states_S_state1)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_state0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states_S_state1)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_HASH qMexuiO6C_SHOSQQCC_3by3odasm1z5VRx723zYLVgY

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_ORD 36
#define DT_N_S_cpus_S_power_states_ORD_STR_SORTABLE 00036

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_REQUIRES_ORDS \
	35, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_SUPPORTS_ORDS \
	37, /* /cpus/power-states/state0 */ \
	38, /* /cpus/power-states/state1 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_REG_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/power-states/state0
 *
 * Node identifier: DT_N_S_cpus_S_power_states_S_state0
 *
 * Binding (compatible = zephyr,power-state):
 *   $ZEPHYR_BASE/dts/bindings/power/zephyr,power-state.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_S_state0_PATH "/cpus/power-states/state0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_S_state0_FULL_NAME "state0"
#define DT_N_S_cpus_S_power_states_S_state0_FULL_NAME_UNQUOTED state0
#define DT_N_S_cpus_S_power_states_S_state0_FULL_NAME_TOKEN state0
#define DT_N_S_cpus_S_power_states_S_state0_FULL_NAME_UPPER_TOKEN STATE0

/* Node parent (/cpus/power-states) identifier: */
#define DT_N_S_cpus_S_power_states_S_state0_PARENT DT_N_S_cpus_S_power_states

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_S_state0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_S_state0_NODELABEL_NUM 1
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_NODELABEL(fn) fn(stop0)
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_NODELABEL_VARGS(fn, ...) fn(stop0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_S_state0_CHILD_NUM 0
#define DT_N_S_cpus_S_power_states_S_state0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_S_state0_HASH 7gm1YoDC64qAH_XbCVglhJihgirY8BmBcJS3HmCqr7E

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_S_state0_ORD 37
#define DT_N_S_cpus_S_power_states_S_state0_ORD_STR_SORTABLE 00037

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_S_state0_REQUIRES_ORDS \
	36, /* /cpus/power-states */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_S_state0_SUPPORTS_ORDS \
	39, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_S_state0_EXISTS 1
#define DT_N_INST_0_zephyr_power_state DT_N_S_cpus_S_power_states_S_state0
#define DT_N_NODELABEL_stop0           DT_N_S_cpus_S_power_states_S_state0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_S_state0_REG_NUM 0
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_state0_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_S_state0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_S_state0_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_S_state0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_S_state0_COMPAT_MATCHES_zephyr_power_state 1
#define DT_N_S_cpus_S_power_states_S_state0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_cpus_S_power_states_S_state0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_COMPAT_MODEL_IDX_0 "power-state"
#define DT_N_S_cpus_S_power_states_S_state0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_S_state0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name "suspend-to-idle"
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_STRING_UNQUOTED suspend-to-idle
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_STRING_TOKEN suspend_to_idle
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_STRING_UPPER_TOKEN SUSPEND_TO_IDLE
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_IDX_0 "suspend-to-idle"
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_IDX_0_ENUM_IDX 2
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_IDX_0_ENUM_VAL_suspend_to_idle_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_ENUM_VAL_suspend_to_idle_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_power_states_S_state0, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_state0, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_state0, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_state0, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_LEN 1
#define DT_N_S_cpus_S_power_states_S_state0_P_power_state_name_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_P_substate_id 1
#define DT_N_S_cpus_S_power_states_S_state0_P_substate_id_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_P_min_residency_us 20
#define DT_N_S_cpus_S_power_states_S_state0_P_min_residency_us_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state0_P_zephyr_pm_device_disabled 0
#define DT_N_S_cpus_S_power_states_S_state0_P_zephyr_pm_device_disabled_EXISTS 1

/*
 * Devicetree node: /cpus/power-states/state1
 *
 * Node identifier: DT_N_S_cpus_S_power_states_S_state1
 *
 * Binding (compatible = zephyr,power-state):
 *   $ZEPHYR_BASE/dts/bindings/power/zephyr,power-state.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_S_state1_PATH "/cpus/power-states/state1"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_S_state1_FULL_NAME "state1"
#define DT_N_S_cpus_S_power_states_S_state1_FULL_NAME_UNQUOTED state1
#define DT_N_S_cpus_S_power_states_S_state1_FULL_NAME_TOKEN state1
#define DT_N_S_cpus_S_power_states_S_state1_FULL_NAME_UPPER_TOKEN STATE1

/* Node parent (/cpus/power-states) identifier: */
#define DT_N_S_cpus_S_power_states_S_state1_PARENT DT_N_S_cpus_S_power_states

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_S_state1_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_S_state1_NODELABEL_NUM 1
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_NODELABEL(fn) fn(stop1)
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_NODELABEL_VARGS(fn, ...) fn(stop1, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_S_state1_CHILD_NUM 0
#define DT_N_S_cpus_S_power_states_S_state1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_S_state1_HASH HNV4Y3tkieq567WGGXTiZXOQ_iS0j5zVpLHTSMEzQPc

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_S_state1_ORD 38
#define DT_N_S_cpus_S_power_states_S_state1_ORD_STR_SORTABLE 00038

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_S_state1_REQUIRES_ORDS \
	36, /* /cpus/power-states */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_S_state1_SUPPORTS_ORDS \
	39, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_S_state1_EXISTS 1
#define DT_N_INST_1_zephyr_power_state DT_N_S_cpus_S_power_states_S_state1
#define DT_N_NODELABEL_stop1           DT_N_S_cpus_S_power_states_S_state1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_S_state1_REG_NUM 0
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_state1_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_S_state1_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_S_state1_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_S_state1_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_S_state1_COMPAT_MATCHES_zephyr_power_state 1
#define DT_N_S_cpus_S_power_states_S_state1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_cpus_S_power_states_S_state1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_COMPAT_MODEL_IDX_0 "power-state"
#define DT_N_S_cpus_S_power_states_S_state1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_S_state1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name "suspend-to-idle"
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_STRING_UNQUOTED suspend-to-idle
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_STRING_TOKEN suspend_to_idle
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_STRING_UPPER_TOKEN SUSPEND_TO_IDLE
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_IDX_0 "suspend-to-idle"
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_IDX_0_ENUM_IDX 2
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_IDX_0_ENUM_VAL_suspend_to_idle_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_ENUM_VAL_suspend_to_idle_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_power_states_S_state1, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_state1, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_state1, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_state1, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_LEN 1
#define DT_N_S_cpus_S_power_states_S_state1_P_power_state_name_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_P_substate_id 2
#define DT_N_S_cpus_S_power_states_S_state1_P_substate_id_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_P_min_residency_us 100
#define DT_N_S_cpus_S_power_states_S_state1_P_min_residency_us_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_state1_P_zephyr_pm_device_disabled 0
#define DT_N_S_cpus_S_power_states_S_state1_P_zephyr_pm_device_disabled_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m4f):
 *   $ZEPHYR_BASE/dts/bindings/cpu/arm,cortex-m4f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UNQUOTED cpu@0
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_TOKEN cpu_0
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UPPER_TOKEN CPU_0

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL(fn) fn(cpu0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpu0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_cpu_0_HASH Su0JBbOtM0QIxe_1ka2Xvgw4rk1QaIlMIj8Rp_v4yVQ

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 39
#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00039

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	35, /* /cpus */ \
	37, /* /cpus/power-states/state0 */ \
	38, /* /cpus/power-states/state1 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m4f DT_N_S_cpus_S_cpu_0
#define DT_N_NODELABEL_cpu0        DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG(fn) fn(DT_N_S_cpus_S_cpu_0, 0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, 0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m4f 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m4f"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0 DT_N_S_cpus_S_power_states_S_state0
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0_PH DT_N_S_cpus_S_power_states_S_state0
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_1 DT_N_S_cpus_S_power_states_S_state1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_1_PH DT_N_S_cpus_S_power_states_S_state1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0) \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0, __VA_ARGS__) \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_LEN 2
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m4f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m4f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m4f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m4f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M4F
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_dma_coherent 0
#define DT_N_S_cpus_S_cpu_0_P_dma_coherent_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48000800
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_PATH "/soc/pin-controller@48000000/gpio@48000800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FULL_NAME "gpio@48000800"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FULL_NAME_UNQUOTED gpio@48000800
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FULL_NAME_TOKEN gpio_48000800
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FULL_NAME_UPPER_TOKEN GPIO_48000800

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_NODELABEL(fn) fn(gpioc)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioc, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_HASH n93nuZdYqflv0mYVUTrRbgKodqnVfp68rXG3AhQJioc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_ORD 40
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_ORD_STR_SORTABLE 00040

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_SUPPORTS_ORDS \
	41, /* /gpio_keys */ \
	42, /* /gpio_keys/button */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_EXISTS 1
#define DT_N_INST_2_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_NODELABEL_gpioc      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_REG_IDX_0_VAL_ADDRESS 1207961600 /* 0x48000800 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_reg {1207961600 /* 0x48000800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_reg_IDX_0 1207961600
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_VAL_bits 4
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /gpio_keys
 *
 * Node identifier: DT_N_S_gpio_keys
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE/dts/bindings/input/gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpio_keys_PATH "/gpio_keys"

/* Node's name with unit-address: */
#define DT_N_S_gpio_keys_FULL_NAME "gpio_keys"
#define DT_N_S_gpio_keys_FULL_NAME_UNQUOTED gpio_keys
#define DT_N_S_gpio_keys_FULL_NAME_TOKEN gpio_keys
#define DT_N_S_gpio_keys_FULL_NAME_UPPER_TOKEN GPIO_KEYS

/* Node parent (/) identifier: */
#define DT_N_S_gpio_keys_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_gpio_keys_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_gpio_keys_NODELABEL_NUM 0
#define DT_N_S_gpio_keys_FOREACH_NODELABEL(fn) 
#define DT_N_S_gpio_keys_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_gpio_keys_CHILD_NUM 1
#define DT_N_S_gpio_keys_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_gpio_keys_FOREACH_CHILD(fn) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_gpio_keys_HASH o_cyM_1oGxkDdZvjWwmF_qWSV_TFQR0RmVqGE69cQ78

/* Node's dependency ordinal: */
#define DT_N_S_gpio_keys_ORD 41
#define DT_N_S_gpio_keys_ORD_STR_SORTABLE 00041

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpio_keys_REQUIRES_ORDS \
	0, /* / */ \
	40, /* /soc/pin-controller@48000000/gpio@48000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpio_keys_SUPPORTS_ORDS \
	42, /* /gpio_keys/button */

/* Existence and alternate IDs: */
#define DT_N_S_gpio_keys_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_gpio_keys

/* Macros for properties that are special in the specification: */
#define DT_N_S_gpio_keys_REG_NUM 0
#define DT_N_S_gpio_keys_FOREACH_REG(fn) 
#define DT_N_S_gpio_keys_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_gpio_keys_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_gpio_keys_RANGES_NUM 0
#define DT_N_S_gpio_keys_FOREACH_RANGE(fn) 
#define DT_N_S_gpio_keys_IRQ_NUM 0
#define DT_N_S_gpio_keys_IRQ_LEVEL 0
#define DT_N_S_gpio_keys_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_gpio_keys_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_gpio_keys_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_gpio_keys_P_debounce_interval_ms 30
#define DT_N_S_gpio_keys_P_debounce_interval_ms_EXISTS 1
#define DT_N_S_gpio_keys_P_polling_mode 0
#define DT_N_S_gpio_keys_P_polling_mode_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action "disconnect-with-pupd"
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_STRING_UNQUOTED disconnect-with-pupd
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_STRING_TOKEN disconnect_with_pupd
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_STRING_UPPER_TOKEN DISCONNECT_WITH_PUPD
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0 "disconnect-with-pupd"
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0_ENUM_IDX 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_IDX_0_ENUM_VAL_disconnect_with_pupd_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_ENUM_VAL_disconnect_with_pupd_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys, zephyr_suspend_action, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_LEN 1
#define DT_N_S_gpio_keys_P_zephyr_suspend_action_EXISTS 1
#define DT_N_S_gpio_keys_P_compatible {"gpio-keys"}
#define DT_N_S_gpio_keys_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys
#define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_TOKEN gpio_keys
#define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys, compatible, 0)
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys, compatible, 0)
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys, compatible, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys, compatible, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_P_compatible_LEN 1
#define DT_N_S_gpio_keys_P_compatible_EXISTS 1
#define DT_N_S_gpio_keys_P_dma_coherent 0
#define DT_N_S_gpio_keys_P_dma_coherent_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_deferred_init 0
#define DT_N_S_gpio_keys_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_gpio_keys_P_wakeup_source 0
#define DT_N_S_gpio_keys_P_wakeup_source_EXISTS 1
#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /gpio_keys/button
 *
 * Node identifier: DT_N_S_gpio_keys_S_button
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_gpio_keys_S_button_PATH "/gpio_keys/button"

/* Node's name with unit-address: */
#define DT_N_S_gpio_keys_S_button_FULL_NAME "button"
#define DT_N_S_gpio_keys_S_button_FULL_NAME_UNQUOTED button
#define DT_N_S_gpio_keys_S_button_FULL_NAME_TOKEN button
#define DT_N_S_gpio_keys_S_button_FULL_NAME_UPPER_TOKEN BUTTON

/* Node parent (/gpio_keys) identifier: */
#define DT_N_S_gpio_keys_S_button_PARENT DT_N_S_gpio_keys

/* Node's index in its parent's list of children: */
#define DT_N_S_gpio_keys_S_button_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_gpio_keys_S_button_NODELABEL_NUM 1
#define DT_N_S_gpio_keys_S_button_FOREACH_NODELABEL(fn) fn(user_button)
#define DT_N_S_gpio_keys_S_button_FOREACH_NODELABEL_VARGS(fn, ...) fn(user_button, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_FOREACH_ANCESTOR(fn) fn(DT_N_S_gpio_keys) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_gpio_keys_S_button_CHILD_NUM 0
#define DT_N_S_gpio_keys_S_button_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD(fn) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_gpio_keys_S_button_HASH xGyp172f7ymL2kzXZ3NEGIppYDK1YGb1Ay3RG1U6EkA

/* Node's dependency ordinal: */
#define DT_N_S_gpio_keys_S_button_ORD 42
#define DT_N_S_gpio_keys_S_button_ORD_STR_SORTABLE 00042

/* Ordinals for what this node depends on directly: */
#define DT_N_S_gpio_keys_S_button_REQUIRES_ORDS \
	40, /* /soc/pin-controller@48000000/gpio@48000800 */ \
	41, /* /gpio_keys */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_gpio_keys_S_button_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_gpio_keys_S_button_EXISTS 1
#define DT_N_ALIAS_sw0             DT_N_S_gpio_keys_S_button
#define DT_N_NODELABEL_user_button DT_N_S_gpio_keys_S_button

/* Macros for properties that are special in the specification: */
#define DT_N_S_gpio_keys_S_button_REG_NUM 0
#define DT_N_S_gpio_keys_S_button_FOREACH_REG(fn) 
#define DT_N_S_gpio_keys_S_button_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_gpio_keys_S_button_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_gpio_keys_S_button_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_gpio_keys_S_button_RANGES_NUM 0
#define DT_N_S_gpio_keys_S_button_FOREACH_RANGE(fn) 
#define DT_N_S_gpio_keys_S_button_IRQ_NUM 0
#define DT_N_S_gpio_keys_S_button_IRQ_LEVEL 0
#define DT_N_S_gpio_keys_S_button_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_gpio_keys_S_button_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_pin 13
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_gpio_keys_S_button, gpios, 0, pin) \
	fn(DT_N_S_gpio_keys_S_button, gpios, 0, flags)
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_gpio_keys_S_button, gpios, 0, flags)
#define DT_N_S_gpio_keys_S_button_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys_S_button, gpios, 0)
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button, gpios, 0)
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, gpios, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, gpios, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_gpios_LEN 1
#define DT_N_S_gpio_keys_S_button_P_gpios_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_label "User"
#define DT_N_S_gpio_keys_S_button_P_label_STRING_UNQUOTED User
#define DT_N_S_gpio_keys_S_button_P_label_STRING_TOKEN User
#define DT_N_S_gpio_keys_S_button_P_label_STRING_UPPER_TOKEN USER
#define DT_N_S_gpio_keys_S_button_P_label_IDX_0 "User"
#define DT_N_S_gpio_keys_S_button_P_label_IDX_0_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys_S_button, label, 0)
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys_S_button, label, 0)
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys_S_button, label, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_keys_S_button, label, 0, __VA_ARGS__)
#define DT_N_S_gpio_keys_S_button_P_label_LEN 1
#define DT_N_S_gpio_keys_S_button_P_label_EXISTS 1
#define DT_N_S_gpio_keys_S_button_P_zephyr_code 11
#define DT_N_S_gpio_keys_S_button_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48000000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_PATH "/soc/pin-controller@48000000/gpio@48000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FULL_NAME "gpio@48000000"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FULL_NAME_UNQUOTED gpio@48000000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FULL_NAME_TOKEN gpio_48000000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FULL_NAME_UPPER_TOKEN GPIO_48000000

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_NODELABEL(fn) fn(gpioa)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioa, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_HASH ktVyE2z0pcWLY1c5JP3x222NkMrJWrY5pPGg8ffd9nE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_ORD 43
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_ORD_STR_SORTABLE 00043

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_SUPPORTS_ORDS \
	44, /* /leds */ \
	45, /* /leds/led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_EXISTS 1
#define DT_N_INST_0_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_NODELABEL_gpioa      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_REG_IDX_0_VAL_ADDRESS 1207959552 /* 0x48000000 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_reg {1207959552 /* 0x48000000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_reg_IDX_0 1207959552
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node's name with unit-address: */
#define DT_N_S_leds_FULL_NAME "leds"
#define DT_N_S_leds_FULL_NAME_UNQUOTED leds
#define DT_N_S_leds_FULL_NAME_TOKEN leds
#define DT_N_S_leds_FULL_NAME_UPPER_TOKEN LEDS

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_NODELABEL_NUM 1
#define DT_N_S_leds_FOREACH_NODELABEL(fn) fn(leds)
#define DT_N_S_leds_FOREACH_NODELABEL_VARGS(fn, ...) fn(leds, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_CHILD_NUM 1
#define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_leds_HASH bMroFUocDdjE3kJ38dK18mDvlCOPoyya5kIIs76irj8

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 44
#define DT_N_S_leds_ORD_STR_SORTABLE 00044

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */ \
	43, /* /soc/pin-controller@48000000/gpio@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	45, /* /leds/led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds
#define DT_N_NODELABEL_leds   DT_N_S_leds

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_FOREACH_REG(fn) 
#define DT_N_S_leds_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_RANGES_NUM 0
#define DT_N_S_leds_FOREACH_RANGE(fn) 
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_IRQ_LEVEL 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node identifier: DT_N_S_leds_S_led_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_0_PATH "/leds/led_0"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_0_FULL_NAME "led_0"
#define DT_N_S_leds_S_led_0_FULL_NAME_UNQUOTED led_0
#define DT_N_S_leds_S_led_0_FULL_NAME_TOKEN led_0
#define DT_N_S_leds_S_led_0_FULL_NAME_UPPER_TOKEN LED_0

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_0_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_0_FOREACH_NODELABEL(fn) fn(green_led)
#define DT_N_S_leds_S_led_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(green_led, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_0_CHILD_NUM 0
#define DT_N_S_leds_S_led_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_leds_S_led_0_HASH kqSZv01Dnr_1hPdmxPVlr9u8kLMk_UWHIyVHG3GknSY

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_0_ORD 45
#define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00045

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
	43, /* /soc/pin-controller@48000000/gpio@48000000 */ \
	44, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0          DT_N_S_leds_S_led_0
#define DT_N_ALIAS_mcuboot_led0  DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_green_led DT_N_S_leds_S_led_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_REG(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_RANGES_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 5
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 0
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_leds_S_led_0, gpios, 0, pin) \
	fn(DT_N_S_leds_S_led_0, gpios, 0, flags)
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, gpios, 0, flags)
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "User LD2"
#define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED User LD2
#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN User_LD2
#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN USER_LD2
#define DT_N_S_leds_S_led_0_P_label_IDX_0 "User LD2"
#define DT_N_S_leds_S_led_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_LEN 1
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /soc/rcc@40021000/reset-controller
 *
 * Node identifier: DT_N_S_soc_S_rcc_40021000_S_reset_controller
 *
 * Binding (compatible = st,stm32-rcc-rctl):
 *   $ZEPHYR_BASE/dts/bindings/reset/st,stm32-rcc-rctl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_PATH "/soc/rcc@40021000/reset-controller"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FULL_NAME "reset-controller"
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FULL_NAME_UNQUOTED reset-controller
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FULL_NAME_TOKEN reset_controller
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FULL_NAME_UPPER_TOKEN RESET_CONTROLLER

/* Node parent (/soc/rcc@40021000) identifier: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_PARENT DT_N_S_soc_S_rcc_40021000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_NODELABEL_NUM 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_NODELABEL(fn) fn(rctl)
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(rctl, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_rcc_40021000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_CHILD_NUM 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_HASH IG1ObzgWVlEiYIYYv8tGMqRz03UFbMoci7_3L65c4dQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_ORD 46
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_ORD_STR_SORTABLE 00046

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_SUPPORTS_ORDS \
	47, /* /soc/timers@40000000 */ \
	56, /* /soc/crc@40023000 */ \
	71, /* /soc/serial@40004400 */ \
	72, /* /soc/serial@40004800 */ \
	73, /* /soc/serial@40004c00 */ \
	76, /* /soc/serial@40008000 */ \
	79, /* /soc/serial@40013800 */ \
	96, /* /soc/timers@40007c00 */ \
	115, /* /soc/timers@40000400 */ \
	119, /* /soc/timers@40000800 */ \
	123, /* /soc/timers@40001000 */ \
	125, /* /soc/timers@40001400 */ \
	127, /* /soc/timers@40012c00 */ \
	131, /* /soc/timers@40013400 */ \
	135, /* /soc/timers@40014000 */ \
	138, /* /soc/timers@40014400 */ \
	141, /* /soc/timers@40014800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_EXISTS 1
#define DT_N_INST_0_st_stm32_rcc_rctl DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_NODELABEL_rctl           DT_N_S_soc_S_rcc_40021000_S_reset_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_REG_NUM 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_REG(fn) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_RANGES_NUM 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_IRQ_NUM 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_IRQ_LEVEL 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_COMPAT_MATCHES_st_stm32_rcc_rctl 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_COMPAT_MODEL_IDX_0 "stm32-rcc-rctl"
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_set_bit_to_deassert 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_set_bit_to_deassert_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible {"st,stm32-rcc-rctl"}
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_IDX_0 "st,stm32-rcc-rctl"
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rcc-rctl
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_IDX_0_STRING_TOKEN st_stm32_rcc_rctl
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RCC_RCTL
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, compatible, 0)
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, compatible, 0)
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_LEN 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_dma_coherent 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_wakeup_source 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rcc_40021000_S_reset_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_PATH "/soc/timers@40000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_FULL_NAME "timers@40000000"
#define DT_N_S_soc_S_timers_40000000_FULL_NAME_UNQUOTED timers@40000000
#define DT_N_S_soc_S_timers_40000000_FULL_NAME_TOKEN timers_40000000
#define DT_N_S_soc_S_timers_40000000_FULL_NAME_UPPER_TOKEN TIMERS_40000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_CHILD_IDX 26

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000000_FOREACH_NODELABEL(fn) fn(timers2)
#define DT_N_S_soc_S_timers_40000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers2, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_qdec)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_qdec)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000000_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_HASH EG81bdVGBcHLEHOWL0pmGPFAUziNY8yKUHEsHXKaWCc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_ORD 47
#define DT_N_S_soc_S_timers_40000000_ORD_STR_SORTABLE 00047

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_SUPPORTS_ORDS \
	49, /* /soc/timers@40000000/pwm */ \
	113, /* /soc/timers@40000000/counter */ \
	114, /* /soc/timers@40000000/qdec */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_EXISTS 1
#define DT_N_INST_0_st_stm32_timers DT_N_S_soc_S_timers_40000000
#define DT_N_NODELABEL_timers2      DT_N_S_soc_S_timers_40000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_REG_NUM 1
#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_ADDRESS 1073741824 /* 0x40000000 */
#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000000, 0)
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, 0)
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_P_reg {1073741824 /* 0x40000000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0 1073741824
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bus 9
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1)
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1)
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id 1792
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000000, resets, 0, id)
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, resets, 0, id)
#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, resets, 0)
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, resets, 0)
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status "okay"
#define DT_N_S_soc_S_timers_40000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_timers_40000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_timers_40000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, status, 0)
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, status, 0)
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupts {28 /* 0x1c */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/tim2_ch1_pa5
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_PATH "/soc/pin-controller@48000000/tim2_ch1_pa5"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FULL_NAME "tim2_ch1_pa5"
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FULL_NAME_UNQUOTED tim2_ch1_pa5
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FULL_NAME_TOKEN tim2_ch1_pa5
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FULL_NAME_UPPER_TOKEN TIM2_CH1_PA5

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_NODELABEL(fn) fn(tim2_ch1_pa5)
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_NODELABEL_VARGS(fn, ...) fn(tim2_ch1_pa5, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_HASH mA84Wc8dcieFtrWdrFiCS6N7UK7LDXfKx2TB_WXPvrc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_ORD 48
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_ORD_STR_SORTABLE 00048

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_SUPPORTS_ORDS \
	49, /* /soc/timers@40000000/pwm */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_EXISTS 1
#define DT_N_NODELABEL_tim2_ch1_pa5 DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_pinmux 161
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_PATH "/soc/timers@40000000/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000000) identifier: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_PARENT DT_N_S_soc_S_timers_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_NODELABEL(fn) fn(pwm2)
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) fn(pwm2, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_HASH EPAdjmCelZ_p_2x7j2JfW0691g5_Ul9BLhqJG9tnJMk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD 49
#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD_STR_SORTABLE 00049

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_REQUIRES_ORDS \
	47, /* /soc/timers@40000000 */ \
	48, /* /soc/pin-controller@48000000/tim2_ch1_pa5 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_SUPPORTS_ORDS \
	50, /* /pwmleds */ \
	51, /* /pwmleds/green_pwm_led */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_EXISTS 1
#define DT_N_INST_0_st_stm32_pwm DT_N_S_soc_S_timers_40000000_S_pwm
#define DT_N_NODELABEL_pwm2      DT_N_S_soc_S_timers_40000000_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000000_S_pwm_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_NUM 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_0, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_0, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_names, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_names, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status "okay"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /pwmleds
 *
 * Node identifier: DT_N_S_pwmleds
 *
 * Binding (compatible = pwm-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/pwm-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pwmleds_PATH "/pwmleds"

/* Node's name with unit-address: */
#define DT_N_S_pwmleds_FULL_NAME "pwmleds"
#define DT_N_S_pwmleds_FULL_NAME_UNQUOTED pwmleds
#define DT_N_S_pwmleds_FULL_NAME_TOKEN pwmleds
#define DT_N_S_pwmleds_FULL_NAME_UPPER_TOKEN PWMLEDS

/* Node parent (/) identifier: */
#define DT_N_S_pwmleds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pwmleds_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_pwmleds_NODELABEL_NUM 0
#define DT_N_S_pwmleds_FOREACH_NODELABEL(fn) 
#define DT_N_S_pwmleds_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pwmleds_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pwmleds_CHILD_NUM 1
#define DT_N_S_pwmleds_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pwmleds_FOREACH_CHILD(fn) fn(DT_N_S_pwmleds_S_green_pwm_led)
#define DT_N_S_pwmleds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pwmleds_S_green_pwm_led)
#define DT_N_S_pwmleds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_green_pwm_led, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_green_pwm_led, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pwmleds_S_green_pwm_led)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pwmleds_S_green_pwm_led)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_green_pwm_led, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_green_pwm_led, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pwmleds_HASH LAVLDxln4k2d8rWkHY5gWY_V_wbRKRVUOItR1NgXPw4

/* Node's dependency ordinal: */
#define DT_N_S_pwmleds_ORD 50
#define DT_N_S_pwmleds_ORD_STR_SORTABLE 00050

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pwmleds_REQUIRES_ORDS \
	0, /* / */ \
	49, /* /soc/timers@40000000/pwm */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pwmleds_SUPPORTS_ORDS \
	51, /* /pwmleds/green_pwm_led */

/* Existence and alternate IDs: */
#define DT_N_S_pwmleds_EXISTS 1
#define DT_N_INST_0_pwm_leds DT_N_S_pwmleds

/* Macros for properties that are special in the specification: */
#define DT_N_S_pwmleds_REG_NUM 0
#define DT_N_S_pwmleds_FOREACH_REG(fn) 
#define DT_N_S_pwmleds_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pwmleds_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pwmleds_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pwmleds_RANGES_NUM 0
#define DT_N_S_pwmleds_FOREACH_RANGE(fn) 
#define DT_N_S_pwmleds_IRQ_NUM 0
#define DT_N_S_pwmleds_IRQ_LEVEL 0
#define DT_N_S_pwmleds_COMPAT_MATCHES_pwm_leds 1
#define DT_N_S_pwmleds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pwmleds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pwmleds_P_compatible {"pwm-leds"}
#define DT_N_S_pwmleds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pwmleds_P_compatible_IDX_0 "pwm-leds"
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UNQUOTED pwm-leds
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_TOKEN pwm_leds
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_LEDS
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds, compatible, 0)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds, compatible, 0)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_P_compatible_LEN 1
#define DT_N_S_pwmleds_P_compatible_EXISTS 1
#define DT_N_S_pwmleds_P_dma_coherent 0
#define DT_N_S_pwmleds_P_dma_coherent_EXISTS 1
#define DT_N_S_pwmleds_P_zephyr_deferred_init 0
#define DT_N_S_pwmleds_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_pwmleds_P_wakeup_source 0
#define DT_N_S_pwmleds_P_wakeup_source_EXISTS 1
#define DT_N_S_pwmleds_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_pwmleds_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /pwmleds/green_pwm_led
 *
 * Node identifier: DT_N_S_pwmleds_S_green_pwm_led
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pwmleds_S_green_pwm_led_PATH "/pwmleds/green_pwm_led"

/* Node's name with unit-address: */
#define DT_N_S_pwmleds_S_green_pwm_led_FULL_NAME "green_pwm_led"
#define DT_N_S_pwmleds_S_green_pwm_led_FULL_NAME_UNQUOTED green_pwm_led
#define DT_N_S_pwmleds_S_green_pwm_led_FULL_NAME_TOKEN green_pwm_led
#define DT_N_S_pwmleds_S_green_pwm_led_FULL_NAME_UPPER_TOKEN GREEN_PWM_LED

/* Node parent (/pwmleds) identifier: */
#define DT_N_S_pwmleds_S_green_pwm_led_PARENT DT_N_S_pwmleds

/* Node's index in its parent's list of children: */
#define DT_N_S_pwmleds_S_green_pwm_led_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pwmleds_S_green_pwm_led_NODELABEL_NUM 1
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_NODELABEL(fn) fn(green_pwm_led)
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_NODELABEL_VARGS(fn, ...) fn(green_pwm_led, __VA_ARGS__)
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_ANCESTOR(fn) fn(DT_N_S_pwmleds) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pwmleds_S_green_pwm_led_CHILD_NUM 0
#define DT_N_S_pwmleds_S_green_pwm_led_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD(fn) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pwmleds_S_green_pwm_led_HASH FeHwFSz5luXjNRyyYg8WsSnP1L7j7jAP0FZZFckLuZw

/* Node's dependency ordinal: */
#define DT_N_S_pwmleds_S_green_pwm_led_ORD 51
#define DT_N_S_pwmleds_S_green_pwm_led_ORD_STR_SORTABLE 00051

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pwmleds_S_green_pwm_led_REQUIRES_ORDS \
	49, /* /soc/timers@40000000/pwm */ \
	50, /* /pwmleds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pwmleds_S_green_pwm_led_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pwmleds_S_green_pwm_led_EXISTS 1
#define DT_N_ALIAS_pwm_led0          DT_N_S_pwmleds_S_green_pwm_led
#define DT_N_NODELABEL_green_pwm_led DT_N_S_pwmleds_S_green_pwm_led

/* Macros for properties that are special in the specification: */
#define DT_N_S_pwmleds_S_green_pwm_led_REG_NUM 0
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_REG(fn) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pwmleds_S_green_pwm_led_RANGES_NUM 0
#define DT_N_S_pwmleds_S_green_pwm_led_FOREACH_RANGE(fn) 
#define DT_N_S_pwmleds_S_green_pwm_led_IRQ_NUM 0
#define DT_N_S_pwmleds_S_green_pwm_led_IRQ_LEVEL 0
#define DT_N_S_pwmleds_S_green_pwm_led_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pwmleds_S_green_pwm_led_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_EXISTS 1
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_PH DT_N_S_soc_S_timers_40000000_S_pwm
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_VAL_channel 1
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_VAL_period 20000000
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_VAL_period_EXISTS 1
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_VAL_flags 0
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, channel) \
	fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, period) \
	fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, flags)
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, period) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, flags)
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_IDX_0_NUM_CELLS 3
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0)
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0)
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_green_pwm_led, pwms, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_LEN 1
#define DT_N_S_pwmleds_S_green_pwm_led_P_pwms_EXISTS 1

/*
 * Devicetree node: /soc/adc@50000100
 *
 * Node identifier: DT_N_S_soc_S_adc_50000100
 *
 * Binding (compatible = st,stm32-adc):
 *   $ZEPHYR_BASE/dts/bindings/adc/st,stm32-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_50000100_PATH "/soc/adc@50000100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_50000100_FULL_NAME "adc@50000100"
#define DT_N_S_soc_S_adc_50000100_FULL_NAME_UNQUOTED adc@50000100
#define DT_N_S_soc_S_adc_50000100_FULL_NAME_TOKEN adc_50000100
#define DT_N_S_soc_S_adc_50000100_FULL_NAME_UPPER_TOKEN ADC_50000100

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_50000100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_50000100_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_50000100_NODELABEL_NUM 1
#define DT_N_S_soc_S_adc_50000100_FOREACH_NODELABEL(fn) fn(adc2)
#define DT_N_S_soc_S_adc_50000100_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc2, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_50000100_CHILD_NUM 0
#define DT_N_S_soc_S_adc_50000100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_50000100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_50000100_HASH LxdlXLvfJsb4AiPhCfDuYI0eWnvRy_vK_dwAyrNtWKo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_50000100_ORD 52
#define DT_N_S_soc_S_adc_50000100_ORD_STR_SORTABLE 00052

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_50000100_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_50000100_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_50000100_EXISTS 1
#define DT_N_INST_1_st_stm32_adc DT_N_S_soc_S_adc_50000100
#define DT_N_NODELABEL_adc2      DT_N_S_soc_S_adc_50000100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_50000100_REG_NUM 1
#define DT_N_S_soc_S_adc_50000100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_REG_IDX_0_VAL_ADDRESS 1342177536 /* 0x50000100 */
#define DT_N_S_soc_S_adc_50000100_REG_IDX_0_VAL_SIZE 256 /* 0x100 */
#define DT_N_S_soc_S_adc_50000100_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_50000100, 0)
#define DT_N_S_soc_S_adc_50000100_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, 0)
#define DT_N_S_soc_S_adc_50000100_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_RANGES_NUM 0
#define DT_N_S_soc_S_adc_50000100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_50000100_IRQ_NUM 1
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_adc_50000100_IRQ_LEVEL 1
#define DT_N_S_soc_S_adc_50000100_COMPAT_MATCHES_st_stm32_adc 1
#define DT_N_S_soc_S_adc_50000100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_adc_50000100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_COMPAT_MODEL_IDX_0 "stm32-adc"
#define DT_N_S_soc_S_adc_50000100_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_50000100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_50000100_P_reg {1342177536 /* 0x50000100 */, 256 /* 0x100 */}
#define DT_N_S_soc_S_adc_50000100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_reg_IDX_0 1342177536
#define DT_N_S_soc_S_adc_50000100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_reg_IDX_1 256
#define DT_N_S_soc_S_adc_50000100_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_VAL_bits 8192
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_50000100, clocks, 0, bus) \
	fn(DT_N_S_soc_S_adc_50000100, clocks, 0, bits)
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, clocks, 0, bits)
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_NAME "adcx"
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_IDX 0
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_50000100, clocks, adcx, bus) \
	fn(DT_N_S_soc_S_adc_50000100, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, clocks, adcx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, clocks, adcx, bits)
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_NUM_CELLS 2
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_VAL_bus DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_VAL_bits DT_N_S_soc_S_adc_50000100_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_adc_50000100_P_clocks_NAME_adcx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, clocks, 0)
#define DT_N_S_soc_S_adc_50000100_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, clocks, 0)
#define DT_N_S_soc_S_adc_50000100_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clock_names {"adcx"}
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clock_names_ENUM_VAL_adcx_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0 "adcx"
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0_STRING_UNQUOTED adcx
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0_STRING_TOKEN adcx
#define DT_N_S_soc_S_adc_50000100_P_clock_names_IDX_0_STRING_UPPER_TOKEN ADCX
#define DT_N_S_soc_S_adc_50000100_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, clock_names, 0)
#define DT_N_S_soc_S_adc_50000100_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, clock_names, 0)
#define DT_N_S_soc_S_adc_50000100_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_clock_names_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_adc_50000100_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_adc_50000100_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_adc_50000100_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_vref_mv 3300
#define DT_N_S_soc_S_adc_50000100_P_vref_mv_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions {12 /* 0xc */, 10 /* 0xa */, 8 /* 0x8 */, 6 /* 0x6 */}
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_0 12
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_1 10
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_2 8
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_IDX_3 6
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 0) \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 1) \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 2) \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 3)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, st_adc_resolutions, 3, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_LEN 4
#define DT_N_S_soc_S_adc_50000100_P_st_adc_resolutions_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times {3 /* 0x3 */, 7 /* 0x7 */, 13 /* 0xd */, 25 /* 0x19 */, 48 /* 0x30 */, 93 /* 0x5d */, 248 /* 0xf8 */, 641 /* 0x281 */}
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_0 3
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_1 7
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_2_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_2 13
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_3_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_3 25
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_4_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_4 48
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_5_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_5 93
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_6_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_6 248
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_7_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_IDX_7 641
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, sampling_times, 0) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 1) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 2) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 3) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 4) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 5) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 6) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 7)
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 7)
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, sampling_times, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_adc_50000100, sampling_times, 7, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_LEN 8
#define DT_N_S_soc_S_adc_50000100_P_sampling_times_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer "programmable"
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_STRING_UNQUOTED programmable
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_STRING_TOKEN programmable
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_STRING_UPPER_TOKEN PROGRAMMABLE
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_IDX_0 "programmable"
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_IDX_0_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_ENUM_VAL_programmable_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, st_adc_sequencer, 0)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_sequencer, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_sequencer_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler "minimal"
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_STRING_UNQUOTED minimal
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_STRING_TOKEN minimal
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_STRING_UPPER_TOKEN MINIMAL
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_IDX_0 "minimal"
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_IDX_0_ENUM_VAL_minimal_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_ENUM_VAL_minimal_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, st_adc_oversampler, 0)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_oversampler, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_oversampler_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator "startup-sw-delay"
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_STRING_UNQUOTED startup-sw-delay
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_STRING_TOKEN startup_sw_delay
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_STRING_UPPER_TOKEN STARTUP_SW_DELAY
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_IDX_0 "startup-sw-delay"
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_IDX_0_ENUM_VAL_startup_sw_delay_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_ENUM_VAL_startup_sw_delay_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, st_adc_internal_regulator, 0)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, st_adc_internal_regulator, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_internal_regulator_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_deep_powerdown 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_deep_powerdown_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_channel_preselection 0
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_channel_preselection_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_differential_support 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_differential_support_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_injected_support 1
#define DT_N_S_soc_S_adc_50000100_P_st_adc_has_injected_support_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_status "disabled"
#define DT_N_S_soc_S_adc_50000100_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_adc_50000100_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_adc_50000100_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_adc_50000100_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_adc_50000100_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_50000100_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, status, 0)
#define DT_N_S_soc_S_adc_50000100_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, status, 0)
#define DT_N_S_soc_S_adc_50000100_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_status_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_compatible {"st,stm32-adc"}
#define DT_N_S_soc_S_adc_50000100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_compatible_IDX_0 "st,stm32-adc"
#define DT_N_S_soc_S_adc_50000100_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc
#define DT_N_S_soc_S_adc_50000100_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc
#define DT_N_S_soc_S_adc_50000100_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC
#define DT_N_S_soc_S_adc_50000100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_50000100, compatible, 0)
#define DT_N_S_soc_S_adc_50000100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_50000100, compatible, 0)
#define DT_N_S_soc_S_adc_50000100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_50000100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_50000100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_50000100_P_compatible_LEN 1
#define DT_N_S_soc_S_adc_50000100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_dma_coherent 0
#define DT_N_S_soc_S_adc_50000100_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_50000100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_wakeup_source 0
#define DT_N_S_soc_S_adc_50000100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_50000100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_50000100_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/can@40006400
 *
 * Node identifier: DT_N_S_soc_S_can_40006400
 *
 * Binding (compatible = st,stm32-fdcan):
 *   $ZEPHYR_BASE/dts/bindings/can/st,stm32-fdcan.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_can_40006400_PATH "/soc/can@40006400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_can_40006400_FULL_NAME "can@40006400"
#define DT_N_S_soc_S_can_40006400_FULL_NAME_UNQUOTED can@40006400
#define DT_N_S_soc_S_can_40006400_FULL_NAME_TOKEN can_40006400
#define DT_N_S_soc_S_can_40006400_FULL_NAME_UPPER_TOKEN CAN_40006400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_can_40006400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_can_40006400_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_can_40006400_NODELABEL_NUM 1
#define DT_N_S_soc_S_can_40006400_FOREACH_NODELABEL(fn) fn(fdcan1)
#define DT_N_S_soc_S_can_40006400_FOREACH_NODELABEL_VARGS(fn, ...) fn(fdcan1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_can_40006400_CHILD_NUM 0
#define DT_N_S_soc_S_can_40006400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_40006400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_can_40006400_HASH val_iOcNyNmh6jx1XoeAlpOC9DwQRToiiXS2PS43mJQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_can_40006400_ORD 53
#define DT_N_S_soc_S_can_40006400_ORD_STR_SORTABLE 00053

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_can_40006400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_can_40006400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_can_40006400_EXISTS 1
#define DT_N_INST_0_st_stm32_fdcan DT_N_S_soc_S_can_40006400
#define DT_N_NODELABEL_fdcan1      DT_N_S_soc_S_can_40006400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_can_40006400_REG_NUM 2
#define DT_N_S_soc_S_can_40006400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_REG_IDX_0_VAL_ADDRESS 1073767424 /* 0x40006400 */
#define DT_N_S_soc_S_can_40006400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_can_40006400_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_REG_IDX_1_VAL_ADDRESS 1073783808 /* 0x4000a400 */
#define DT_N_S_soc_S_can_40006400_REG_IDX_1_VAL_SIZE 848 /* 0x350 */
#define DT_N_S_soc_S_can_40006400_REG_NAME_m_can_EXISTS 1
#define DT_N_S_soc_S_can_40006400_REG_NAME_m_can_VAL_ADDRESS DT_N_S_soc_S_can_40006400_REG_IDX_0_VAL_ADDRESS
#define DT_N_S_soc_S_can_40006400_REG_NAME_m_can_VAL_SIZE DT_N_S_soc_S_can_40006400_REG_IDX_0_VAL_SIZE
#define DT_N_S_soc_S_can_40006400_REG_NAME_message_ram_EXISTS 1
#define DT_N_S_soc_S_can_40006400_REG_NAME_message_ram_VAL_ADDRESS DT_N_S_soc_S_can_40006400_REG_IDX_1_VAL_ADDRESS
#define DT_N_S_soc_S_can_40006400_REG_NAME_message_ram_VAL_SIZE DT_N_S_soc_S_can_40006400_REG_IDX_1_VAL_SIZE
#define DT_N_S_soc_S_can_40006400_FOREACH_REG(fn) fn(DT_N_S_soc_S_can_40006400, 0) fn(DT_N_S_soc_S_can_40006400, 1)
#define DT_N_S_soc_S_can_40006400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, 0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006400, 1)
#define DT_N_S_soc_S_can_40006400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, 0, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006400, 1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_40006400, 1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_RANGES_NUM 0
#define DT_N_S_soc_S_can_40006400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_can_40006400_IRQ_NUM 2
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_irq 22
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_can_40006400_IRQ_LEVEL 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int0_VAL_irq DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int0_VAL_priority DT_N_S_soc_S_can_40006400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int0_CONTROLLER DT_N_S_soc_S_can_40006400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int1_VAL_irq DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int1_VAL_priority DT_N_S_soc_S_can_40006400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_40006400_IRQ_NAME_int1_CONTROLLER DT_N_S_soc_S_can_40006400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_can_40006400_COMPAT_MATCHES_st_stm32_fdcan 1
#define DT_N_S_soc_S_can_40006400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_can_40006400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_COMPAT_MODEL_IDX_0 "stm32-fdcan"
#define DT_N_S_soc_S_can_40006400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_can_40006400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bits 33554432
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_can_40006400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_can_40006400, clocks, 0, bits)
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, clocks, 0, bits)
#define DT_N_S_soc_S_can_40006400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, clocks, 0)
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, clocks, 0)
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_clocks_LEN 1
#define DT_N_S_soc_S_can_40006400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg {1073767424 /* 0x40006400 */, 1024 /* 0x400 */, 1073783808 /* 0x4000a400 */, 848 /* 0x350 */}
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_0 1073767424
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_2 1073783808
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_IDX_3 848
#define DT_N_S_soc_S_can_40006400_P_reg_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts {21 /* 0x15 */, 0 /* 0x0 */, 22 /* 0x16 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_2 22
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_can_40006400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names {"int0", "int1"}
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0 "int0"
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_STRING_UNQUOTED int0
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_STRING_TOKEN int0
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN INT0
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1 "int1"
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_STRING_UNQUOTED int1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_STRING_TOKEN int1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN INT1
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_can_40006400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg {0 /* 0x0 */, 28 /* 0x1c */, 8 /* 0x8 */, 3 /* 0x3 */, 3 /* 0x3 */, 0 /* 0x0 */, 3 /* 0x3 */, 3 /* 0x3 */}
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_0 0
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_1 28
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_2 8
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_3 3
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_4_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_4 3
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_5_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_5 0
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_6_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_6 3
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_7_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_IDX_7 3
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 0) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 1) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 2) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 3) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 4) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 5) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 6) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 7)
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 7)
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 7, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, bosch_mram_cfg, 7, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_LEN 8
#define DT_N_S_soc_S_can_40006400_P_bosch_mram_cfg_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_timestamp_counter_prescaler 1
#define DT_N_S_soc_S_can_40006400_P_bosch_timestamp_counter_prescaler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_can_40006400_P_bosch_timestamp_counter_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_timestamp_counter_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_timestamp_counter_prescaler_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_bosch_timestamp_counter_prescaler_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status "disabled"
#define DT_N_S_soc_S_can_40006400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_can_40006400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_can_40006400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_can_40006400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, status, 0)
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, status, 0)
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_status_LEN 1
#define DT_N_S_soc_S_can_40006400_P_status_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_compatible {"st,stm32-fdcan"}
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0 "st,stm32-fdcan"
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-fdcan
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_STRING_TOKEN st_stm32_fdcan
#define DT_N_S_soc_S_can_40006400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FDCAN
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, compatible, 0)
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, compatible, 0)
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_compatible_LEN 1
#define DT_N_S_soc_S_can_40006400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_names {"m_can", "message_ram"}
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_0 "m_can"
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_0_STRING_UNQUOTED m_can
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_0_STRING_TOKEN m_can
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_0_STRING_UPPER_TOKEN M_CAN
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_1 "message_ram"
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_1_STRING_UNQUOTED message_ram
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_1_STRING_TOKEN message_ram
#define DT_N_S_soc_S_can_40006400_P_reg_names_IDX_1_STRING_UPPER_TOKEN MESSAGE_RAM
#define DT_N_S_soc_S_can_40006400_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_40006400, reg_names, 0) \
	fn(DT_N_S_soc_S_can_40006400, reg_names, 1)
#define DT_N_S_soc_S_can_40006400_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_40006400, reg_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, reg_names, 1)
#define DT_N_S_soc_S_can_40006400_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_40006400, reg_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_can_40006400, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_40006400, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_can_40006400, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_can_40006400_P_reg_names_LEN 2
#define DT_N_S_soc_S_can_40006400_P_reg_names_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_dma_coherent 0
#define DT_N_S_soc_S_can_40006400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_can_40006400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_wakeup_source 0
#define DT_N_S_soc_S_can_40006400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_can_40006400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_can_40006400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/comparator@40010200
 *
 * Node identifier: DT_N_S_soc_S_comparator_40010200
 *
 * Binding (compatible = st,stm32g4-comp):
 *   $ZEPHYR_BASE/dts/bindings/comparator/st,stm32g4-comp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_comparator_40010200_PATH "/soc/comparator@40010200"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_comparator_40010200_FULL_NAME "comparator@40010200"
#define DT_N_S_soc_S_comparator_40010200_FULL_NAME_UNQUOTED comparator@40010200
#define DT_N_S_soc_S_comparator_40010200_FULL_NAME_TOKEN comparator_40010200
#define DT_N_S_soc_S_comparator_40010200_FULL_NAME_UPPER_TOKEN COMPARATOR_40010200

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_comparator_40010200_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_comparator_40010200_CHILD_IDX 47

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_comparator_40010200_NODELABEL_NUM 1
#define DT_N_S_soc_S_comparator_40010200_FOREACH_NODELABEL(fn) fn(comp1)
#define DT_N_S_soc_S_comparator_40010200_FOREACH_NODELABEL_VARGS(fn, ...) fn(comp1, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_comparator_40010200_CHILD_NUM 0
#define DT_N_S_soc_S_comparator_40010200_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_comparator_40010200_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_comparator_40010200_HASH QQlS8U1q4k2cc_mxFE9mS2KdQ3JbSk9gb6s_zOtqCi8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_comparator_40010200_ORD 54
#define DT_N_S_soc_S_comparator_40010200_ORD_STR_SORTABLE 00054

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_comparator_40010200_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_comparator_40010200_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_comparator_40010200_EXISTS 1
#define DT_N_INST_0_st_stm32g4_comp DT_N_S_soc_S_comparator_40010200
#define DT_N_INST_0_st_stm32_comp   DT_N_S_soc_S_comparator_40010200
#define DT_N_NODELABEL_comp1        DT_N_S_soc_S_comparator_40010200

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_comparator_40010200_REG_NUM 1
#define DT_N_S_soc_S_comparator_40010200_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_REG_IDX_0_VAL_ADDRESS 1073807872 /* 0x40010200 */
#define DT_N_S_soc_S_comparator_40010200_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_comparator_40010200_FOREACH_REG(fn) fn(DT_N_S_soc_S_comparator_40010200, 0)
#define DT_N_S_soc_S_comparator_40010200_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, 0)
#define DT_N_S_soc_S_comparator_40010200_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_RANGES_NUM 0
#define DT_N_S_soc_S_comparator_40010200_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_comparator_40010200_IRQ_NUM 1
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_VAL_irq 64
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_comparator_40010200_IRQ_LEVEL 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_MATCHES_st_stm32g4_comp 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_comparator_40010200_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_MODEL_IDX_0 "stm32g4-comp"
#define DT_N_S_soc_S_comparator_40010200_COMPAT_MATCHES_st_stm32_comp 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_comparator_40010200_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_COMPAT_MODEL_IDX_1 "stm32-comp"
#define DT_N_S_soc_S_comparator_40010200_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_comparator_40010200_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis "NONE"
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_STRING_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_IDX_0 "NONE"
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010200, hysteresis, 0)
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, hysteresis, 0)
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, hysteresis, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, hysteresis, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_LEN 1
#define DT_N_S_soc_S_comparator_40010200_P_hysteresis_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel "NONE"
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_STRING_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_IDX_0 "NONE"
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010200, st_blank_sel, 0)
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, st_blank_sel, 0)
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, st_blank_sel, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, st_blank_sel, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_LEN 1
#define DT_N_S_soc_S_comparator_40010200_P_st_blank_sel_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_miller_effect_hold_disable 0
#define DT_N_S_soc_S_comparator_40010200_P_st_miller_effect_hold_disable_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_reg {1073807872 /* 0x40010200 */, 4 /* 0x4 */}
#define DT_N_S_soc_S_comparator_40010200_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_reg_IDX_0 1073807872
#define DT_N_S_soc_S_comparator_40010200_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_reg_IDX_1 4
#define DT_N_S_soc_S_comparator_40010200_P_reg_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_interrupts {64 /* 0x40 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_comparator_40010200_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_interrupts_IDX_0 64
#define DT_N_S_soc_S_comparator_40010200_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_comparator_40010200_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_comparator_40010200, clocks, 0, bus) \
	fn(DT_N_S_soc_S_comparator_40010200, clocks, 0, bits)
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_comparator_40010200, clocks, 0, bits)
#define DT_N_S_soc_S_comparator_40010200_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_comparator_40010200_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010200, clocks, 0)
#define DT_N_S_soc_S_comparator_40010200_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, clocks, 0)
#define DT_N_S_soc_S_comparator_40010200_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_clocks_LEN 1
#define DT_N_S_soc_S_comparator_40010200_P_clocks_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_invert_output "NONINVERTED"
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_STRING_UNQUOTED NONINVERTED
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_STRING_TOKEN NONINVERTED
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_STRING_UPPER_TOKEN NONINVERTED
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_IDX_0 "NONINVERTED"
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_IDX_0_ENUM_VAL_noninverted_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_ENUM_VAL_noninverted_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010200, invert_output, 0)
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, invert_output, 0)
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, invert_output, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, invert_output, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_LEN 1
#define DT_N_S_soc_S_comparator_40010200_P_invert_output_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_exti_line 21
#define DT_N_S_soc_S_comparator_40010200_P_st_exti_line_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_st_lock_enable 0
#define DT_N_S_soc_S_comparator_40010200_P_st_lock_enable_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_status "disabled"
#define DT_N_S_soc_S_comparator_40010200_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_comparator_40010200_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_comparator_40010200_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_comparator_40010200_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_comparator_40010200_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_comparator_40010200_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010200, status, 0)
#define DT_N_S_soc_S_comparator_40010200_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, status, 0)
#define DT_N_S_soc_S_comparator_40010200_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_status_LEN 1
#define DT_N_S_soc_S_comparator_40010200_P_status_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_compatible {"st,stm32g4-comp", "st,stm32-comp"}
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_0 "st,stm32g4-comp"
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g4-comp
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_0_STRING_TOKEN st_stm32g4_comp
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G4_COMP
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_1 "st,stm32-comp"
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-comp
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_1_STRING_TOKEN st_stm32_comp
#define DT_N_S_soc_S_comparator_40010200_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_COMP
#define DT_N_S_soc_S_comparator_40010200_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010200, compatible, 0) \
	fn(DT_N_S_soc_S_comparator_40010200, compatible, 1)
#define DT_N_S_soc_S_comparator_40010200_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010200, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_comparator_40010200, compatible, 1)
#define DT_N_S_soc_S_comparator_40010200_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010200, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_comparator_40010200, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010200, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_comparator_40010200, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010200_P_compatible_LEN 2
#define DT_N_S_soc_S_comparator_40010200_P_compatible_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_dma_coherent 0
#define DT_N_S_soc_S_comparator_40010200_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_comparator_40010200_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_wakeup_source 0
#define DT_N_S_soc_S_comparator_40010200_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_comparator_40010200_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_comparator_40010200_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/comparator@40010204
 *
 * Node identifier: DT_N_S_soc_S_comparator_40010204
 *
 * Binding (compatible = st,stm32g4-comp):
 *   $ZEPHYR_BASE/dts/bindings/comparator/st,stm32g4-comp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_comparator_40010204_PATH "/soc/comparator@40010204"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_comparator_40010204_FULL_NAME "comparator@40010204"
#define DT_N_S_soc_S_comparator_40010204_FULL_NAME_UNQUOTED comparator@40010204
#define DT_N_S_soc_S_comparator_40010204_FULL_NAME_TOKEN comparator_40010204
#define DT_N_S_soc_S_comparator_40010204_FULL_NAME_UPPER_TOKEN COMPARATOR_40010204

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_comparator_40010204_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_comparator_40010204_CHILD_IDX 48

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_comparator_40010204_NODELABEL_NUM 1
#define DT_N_S_soc_S_comparator_40010204_FOREACH_NODELABEL(fn) fn(comp2)
#define DT_N_S_soc_S_comparator_40010204_FOREACH_NODELABEL_VARGS(fn, ...) fn(comp2, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_comparator_40010204_CHILD_NUM 0
#define DT_N_S_soc_S_comparator_40010204_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_comparator_40010204_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_comparator_40010204_HASH XCEWs4kKtzCfz4hpYp1eSp7j4PMbqXMmBFYzyVJU9ko

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_comparator_40010204_ORD 55
#define DT_N_S_soc_S_comparator_40010204_ORD_STR_SORTABLE 00055

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_comparator_40010204_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_comparator_40010204_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_comparator_40010204_EXISTS 1
#define DT_N_INST_1_st_stm32g4_comp DT_N_S_soc_S_comparator_40010204
#define DT_N_INST_1_st_stm32_comp   DT_N_S_soc_S_comparator_40010204
#define DT_N_NODELABEL_comp2        DT_N_S_soc_S_comparator_40010204

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_comparator_40010204_REG_NUM 1
#define DT_N_S_soc_S_comparator_40010204_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_REG_IDX_0_VAL_ADDRESS 1073807876 /* 0x40010204 */
#define DT_N_S_soc_S_comparator_40010204_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_comparator_40010204_FOREACH_REG(fn) fn(DT_N_S_soc_S_comparator_40010204, 0)
#define DT_N_S_soc_S_comparator_40010204_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, 0)
#define DT_N_S_soc_S_comparator_40010204_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_RANGES_NUM 0
#define DT_N_S_soc_S_comparator_40010204_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_comparator_40010204_IRQ_NUM 1
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_VAL_irq 64
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_comparator_40010204_IRQ_LEVEL 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_MATCHES_st_stm32g4_comp 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_comparator_40010204_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_MODEL_IDX_0 "stm32g4-comp"
#define DT_N_S_soc_S_comparator_40010204_COMPAT_MATCHES_st_stm32_comp 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_comparator_40010204_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_COMPAT_MODEL_IDX_1 "stm32-comp"
#define DT_N_S_soc_S_comparator_40010204_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_comparator_40010204_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis "NONE"
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_STRING_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_IDX_0 "NONE"
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010204, hysteresis, 0)
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, hysteresis, 0)
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, hysteresis, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, hysteresis, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_LEN 1
#define DT_N_S_soc_S_comparator_40010204_P_hysteresis_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel "NONE"
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_STRING_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_IDX_0 "NONE"
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010204, st_blank_sel, 0)
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, st_blank_sel, 0)
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, st_blank_sel, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, st_blank_sel, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_LEN 1
#define DT_N_S_soc_S_comparator_40010204_P_st_blank_sel_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_miller_effect_hold_disable 0
#define DT_N_S_soc_S_comparator_40010204_P_st_miller_effect_hold_disable_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_reg {1073807876 /* 0x40010204 */, 4 /* 0x4 */}
#define DT_N_S_soc_S_comparator_40010204_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_reg_IDX_0 1073807876
#define DT_N_S_soc_S_comparator_40010204_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_reg_IDX_1 4
#define DT_N_S_soc_S_comparator_40010204_P_reg_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_interrupts {64 /* 0x40 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_comparator_40010204_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_interrupts_IDX_0 64
#define DT_N_S_soc_S_comparator_40010204_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_comparator_40010204_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_comparator_40010204, clocks, 0, bus) \
	fn(DT_N_S_soc_S_comparator_40010204, clocks, 0, bits)
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_comparator_40010204, clocks, 0, bits)
#define DT_N_S_soc_S_comparator_40010204_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_comparator_40010204_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010204, clocks, 0)
#define DT_N_S_soc_S_comparator_40010204_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, clocks, 0)
#define DT_N_S_soc_S_comparator_40010204_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_clocks_LEN 1
#define DT_N_S_soc_S_comparator_40010204_P_clocks_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_invert_output "NONINVERTED"
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_STRING_UNQUOTED NONINVERTED
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_STRING_TOKEN NONINVERTED
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_STRING_UPPER_TOKEN NONINVERTED
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_IDX_0 "NONINVERTED"
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_IDX_0_ENUM_VAL_noninverted_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_ENUM_VAL_noninverted_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010204, invert_output, 0)
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, invert_output, 0)
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, invert_output, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, invert_output, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_LEN 1
#define DT_N_S_soc_S_comparator_40010204_P_invert_output_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_exti_line 22
#define DT_N_S_soc_S_comparator_40010204_P_st_exti_line_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_st_lock_enable 0
#define DT_N_S_soc_S_comparator_40010204_P_st_lock_enable_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_status "disabled"
#define DT_N_S_soc_S_comparator_40010204_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_comparator_40010204_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_comparator_40010204_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_comparator_40010204_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_comparator_40010204_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_comparator_40010204_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010204, status, 0)
#define DT_N_S_soc_S_comparator_40010204_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, status, 0)
#define DT_N_S_soc_S_comparator_40010204_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_status_LEN 1
#define DT_N_S_soc_S_comparator_40010204_P_status_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_compatible {"st,stm32g4-comp", "st,stm32-comp"}
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_0 "st,stm32g4-comp"
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g4-comp
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_0_STRING_TOKEN st_stm32g4_comp
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G4_COMP
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_1 "st,stm32-comp"
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-comp
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_1_STRING_TOKEN st_stm32_comp
#define DT_N_S_soc_S_comparator_40010204_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_COMP
#define DT_N_S_soc_S_comparator_40010204_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40010204, compatible, 0) \
	fn(DT_N_S_soc_S_comparator_40010204, compatible, 1)
#define DT_N_S_soc_S_comparator_40010204_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40010204, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_comparator_40010204, compatible, 1)
#define DT_N_S_soc_S_comparator_40010204_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40010204, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_comparator_40010204, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40010204, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_comparator_40010204, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40010204_P_compatible_LEN 2
#define DT_N_S_soc_S_comparator_40010204_P_compatible_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_dma_coherent 0
#define DT_N_S_soc_S_comparator_40010204_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_comparator_40010204_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_wakeup_source 0
#define DT_N_S_soc_S_comparator_40010204_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_comparator_40010204_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_comparator_40010204_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/crc@40023000
 *
 * Node identifier: DT_N_S_soc_S_crc_40023000
 *
 * Binding (compatible = st,stm32-crc):
 *   $ZEPHYR_BASE/dts/bindings/crc/st,stm32-crc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_crc_40023000_PATH "/soc/crc@40023000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_crc_40023000_FULL_NAME "crc@40023000"
#define DT_N_S_soc_S_crc_40023000_FULL_NAME_UNQUOTED crc@40023000
#define DT_N_S_soc_S_crc_40023000_FULL_NAME_TOKEN crc_40023000
#define DT_N_S_soc_S_crc_40023000_FULL_NAME_UPPER_TOKEN CRC_40023000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_crc_40023000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_crc_40023000_CHILD_IDX 49

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_crc_40023000_NODELABEL_NUM 1
#define DT_N_S_soc_S_crc_40023000_FOREACH_NODELABEL(fn) fn(crc)
#define DT_N_S_soc_S_crc_40023000_FOREACH_NODELABEL_VARGS(fn, ...) fn(crc, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_crc_40023000_CHILD_NUM 0
#define DT_N_S_soc_S_crc_40023000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_crc_40023000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_crc_40023000_HASH AHAfoacZs4JRE8pA4wgH8Dgc30qQVb4epHOyLB_o7Aw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_crc_40023000_ORD 56
#define DT_N_S_soc_S_crc_40023000_ORD_STR_SORTABLE 00056

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_crc_40023000_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_crc_40023000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crc_40023000_EXISTS 1
#define DT_N_INST_0_st_stm32_crc DT_N_S_soc_S_crc_40023000
#define DT_N_NODELABEL_crc       DT_N_S_soc_S_crc_40023000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_crc_40023000_REG_NUM 1
#define DT_N_S_soc_S_crc_40023000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_REG_IDX_0_VAL_ADDRESS 1073885184 /* 0x40023000 */
#define DT_N_S_soc_S_crc_40023000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_crc_40023000_FOREACH_REG(fn) fn(DT_N_S_soc_S_crc_40023000, 0)
#define DT_N_S_soc_S_crc_40023000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, 0)
#define DT_N_S_soc_S_crc_40023000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_crc_40023000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crc_40023000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_RANGES_NUM 0
#define DT_N_S_soc_S_crc_40023000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_crc_40023000_IRQ_NUM 0
#define DT_N_S_soc_S_crc_40023000_IRQ_LEVEL 0
#define DT_N_S_soc_S_crc_40023000_COMPAT_MATCHES_st_stm32_crc 1
#define DT_N_S_soc_S_crc_40023000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_crc_40023000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_COMPAT_MODEL_IDX_0 "stm32-crc"
#define DT_N_S_soc_S_crc_40023000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_crc_40023000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_crc_40023000_P_reg {1073885184 /* 0x40023000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_crc_40023000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_reg_IDX_0 1073885184
#define DT_N_S_soc_S_crc_40023000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_crc_40023000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_VAL_bus 72
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_VAL_bits 4096
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_crc_40023000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_crc_40023000, clocks, 0, bits)
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crc_40023000, clocks, 0, bits)
#define DT_N_S_soc_S_crc_40023000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_crc_40023000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crc_40023000, clocks, 0)
#define DT_N_S_soc_S_crc_40023000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, clocks, 0)
#define DT_N_S_soc_S_crc_40023000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crc_40023000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crc_40023000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_clocks_LEN 1
#define DT_N_S_soc_S_crc_40023000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_status "disabled"
#define DT_N_S_soc_S_crc_40023000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_crc_40023000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_crc_40023000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_crc_40023000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_crc_40023000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_crc_40023000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crc_40023000, status, 0)
#define DT_N_S_soc_S_crc_40023000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, status, 0)
#define DT_N_S_soc_S_crc_40023000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crc_40023000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crc_40023000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_status_LEN 1
#define DT_N_S_soc_S_crc_40023000_P_status_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_compatible {"st,stm32-crc"}
#define DT_N_S_soc_S_crc_40023000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_compatible_IDX_0 "st,stm32-crc"
#define DT_N_S_soc_S_crc_40023000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-crc
#define DT_N_S_soc_S_crc_40023000_P_compatible_IDX_0_STRING_TOKEN st_stm32_crc
#define DT_N_S_soc_S_crc_40023000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_CRC
#define DT_N_S_soc_S_crc_40023000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crc_40023000, compatible, 0)
#define DT_N_S_soc_S_crc_40023000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, compatible, 0)
#define DT_N_S_soc_S_crc_40023000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crc_40023000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crc_40023000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_compatible_LEN 1
#define DT_N_S_soc_S_crc_40023000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_dma_coherent 0
#define DT_N_S_soc_S_crc_40023000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_crc_40023000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_wakeup_source 0
#define DT_N_S_soc_S_crc_40023000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_crc_40023000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_VAL_id 1292
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_crc_40023000, resets, 0, id)
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, resets, 0, id)
#define DT_N_S_soc_S_crc_40023000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_crc_40023000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crc_40023000, resets, 0)
#define DT_N_S_soc_S_crc_40023000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crc_40023000, resets, 0)
#define DT_N_S_soc_S_crc_40023000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crc_40023000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crc_40023000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crc_40023000_P_resets_LEN 1
#define DT_N_S_soc_S_crc_40023000_P_resets_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/dac1_out1_pa4
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_PATH "/soc/pin-controller@48000000/dac1_out1_pa4"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FULL_NAME "dac1_out1_pa4"
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FULL_NAME_UNQUOTED dac1_out1_pa4
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FULL_NAME_TOKEN dac1_out1_pa4
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FULL_NAME_UPPER_TOKEN DAC1_OUT1_PA4

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_NODELABEL(fn) fn(dac1_out1_pa4)
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_NODELABEL_VARGS(fn, ...) fn(dac1_out1_pa4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_HASH Xk_AsWAUvpV6bDiRJkg5_xU9REWhrbnp1WhyYTpGkXs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_ORD 57
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_ORD_STR_SORTABLE 00057

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_SUPPORTS_ORDS \
	58, /* /soc/dac@50000800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_EXISTS 1
#define DT_N_NODELABEL_dac1_out1_pa4 DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_pinmux 144
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/dac@50000800
 *
 * Node identifier: DT_N_S_soc_S_dac_50000800
 *
 * Binding (compatible = st,stm32-dac):
 *   $ZEPHYR_BASE/dts/bindings/dac/st,stm32-dac.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dac_50000800_PATH "/soc/dac@50000800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dac_50000800_FULL_NAME "dac@50000800"
#define DT_N_S_soc_S_dac_50000800_FULL_NAME_UNQUOTED dac@50000800
#define DT_N_S_soc_S_dac_50000800_FULL_NAME_TOKEN dac_50000800
#define DT_N_S_soc_S_dac_50000800_FULL_NAME_UPPER_TOKEN DAC_50000800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dac_50000800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dac_50000800_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dac_50000800_NODELABEL_NUM 1
#define DT_N_S_soc_S_dac_50000800_FOREACH_NODELABEL(fn) fn(dac1)
#define DT_N_S_soc_S_dac_50000800_FOREACH_NODELABEL_VARGS(fn, ...) fn(dac1, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dac_50000800_CHILD_NUM 0
#define DT_N_S_soc_S_dac_50000800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dac_50000800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dac_50000800_HASH 9VsAq9JmFP9e7AffHjoM1_sIKPrSz_IklcHnWvAZYrk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dac_50000800_ORD 58
#define DT_N_S_soc_S_dac_50000800_ORD_STR_SORTABLE 00058

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dac_50000800_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */ \
	57, /* /soc/pin-controller@48000000/dac1_out1_pa4 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dac_50000800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dac_50000800_EXISTS 1
#define DT_N_INST_0_st_stm32_dac DT_N_S_soc_S_dac_50000800
#define DT_N_NODELABEL_dac1      DT_N_S_soc_S_dac_50000800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dac_50000800_REG_NUM 1
#define DT_N_S_soc_S_dac_50000800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_REG_IDX_0_VAL_ADDRESS 1342179328 /* 0x50000800 */
#define DT_N_S_soc_S_dac_50000800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dac_50000800_FOREACH_REG(fn) fn(DT_N_S_soc_S_dac_50000800, 0)
#define DT_N_S_soc_S_dac_50000800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, 0)
#define DT_N_S_soc_S_dac_50000800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_RANGES_NUM 0
#define DT_N_S_soc_S_dac_50000800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dac_50000800_IRQ_NUM 0
#define DT_N_S_soc_S_dac_50000800_IRQ_LEVEL 0
#define DT_N_S_soc_S_dac_50000800_COMPAT_MATCHES_st_stm32_dac 1
#define DT_N_S_soc_S_dac_50000800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dac_50000800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_COMPAT_MODEL_IDX_0 "stm32-dac"
#define DT_N_S_soc_S_dac_50000800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dac_50000800_PINCTRL_NUM 1
#define DT_N_S_soc_S_dac_50000800_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_dac_50000800_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_dac_50000800_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_dac_50000800_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4

/* Generic property macros: */
#define DT_N_S_soc_S_dac_50000800_P_reg {1342179328 /* 0x50000800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dac_50000800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_reg_IDX_0 1342179328
#define DT_N_S_soc_S_dac_50000800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dac_50000800_P_reg_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_VAL_bits 65536
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dac_50000800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dac_50000800, clocks, 0, bits)
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dac_50000800, clocks, 0, bits)
#define DT_N_S_soc_S_dac_50000800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dac_50000800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50000800, clocks, 0)
#define DT_N_S_soc_S_dac_50000800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, clocks, 0)
#define DT_N_S_soc_S_dac_50000800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50000800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50000800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_clocks_LEN 1
#define DT_N_S_soc_S_dac_50000800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_status "okay"
#define DT_N_S_soc_S_dac_50000800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_dac_50000800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_dac_50000800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_dac_50000800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_dac_50000800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_dac_50000800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50000800, status, 0)
#define DT_N_S_soc_S_dac_50000800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, status, 0)
#define DT_N_S_soc_S_dac_50000800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50000800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50000800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_status_LEN 1
#define DT_N_S_soc_S_dac_50000800_P_status_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_compatible {"st,stm32-dac"}
#define DT_N_S_soc_S_dac_50000800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_compatible_IDX_0 "st,stm32-dac"
#define DT_N_S_soc_S_dac_50000800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dac
#define DT_N_S_soc_S_dac_50000800_P_compatible_IDX_0_STRING_TOKEN st_stm32_dac
#define DT_N_S_soc_S_dac_50000800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DAC
#define DT_N_S_soc_S_dac_50000800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50000800, compatible, 0)
#define DT_N_S_soc_S_dac_50000800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, compatible, 0)
#define DT_N_S_soc_S_dac_50000800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_compatible_LEN 1
#define DT_N_S_soc_S_dac_50000800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_dma_coherent 0
#define DT_N_S_soc_S_dac_50000800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dac_50000800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_wakeup_source 0
#define DT_N_S_soc_S_dac_50000800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dac_50000800_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50000800, pinctrl_0, 0)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, pinctrl_0, 0)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50000800, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50000800, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50000800, pinctrl_names, 0)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50000800, pinctrl_names, 0)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50000800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50000800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_dac_50000800_P_pinctrl_names_EXISTS 1

/*
 * Devicetree node: /soc/dac@50001000
 *
 * Node identifier: DT_N_S_soc_S_dac_50001000
 *
 * Binding (compatible = st,stm32-dac):
 *   $ZEPHYR_BASE/dts/bindings/dac/st,stm32-dac.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dac_50001000_PATH "/soc/dac@50001000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dac_50001000_FULL_NAME "dac@50001000"
#define DT_N_S_soc_S_dac_50001000_FULL_NAME_UNQUOTED dac@50001000
#define DT_N_S_soc_S_dac_50001000_FULL_NAME_TOKEN dac_50001000
#define DT_N_S_soc_S_dac_50001000_FULL_NAME_UPPER_TOKEN DAC_50001000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dac_50001000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dac_50001000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dac_50001000_NODELABEL_NUM 1
#define DT_N_S_soc_S_dac_50001000_FOREACH_NODELABEL(fn) fn(dac3)
#define DT_N_S_soc_S_dac_50001000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dac3, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dac_50001000_CHILD_NUM 0
#define DT_N_S_soc_S_dac_50001000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dac_50001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dac_50001000_HASH txQsX3nA2GYV7oL_iUQuKB4FDJj1OgdbcKTIQR2tHFs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dac_50001000_ORD 59
#define DT_N_S_soc_S_dac_50001000_ORD_STR_SORTABLE 00059

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dac_50001000_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dac_50001000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dac_50001000_EXISTS 1
#define DT_N_INST_1_st_stm32_dac DT_N_S_soc_S_dac_50001000
#define DT_N_NODELABEL_dac3      DT_N_S_soc_S_dac_50001000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dac_50001000_REG_NUM 1
#define DT_N_S_soc_S_dac_50001000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_REG_IDX_0_VAL_ADDRESS 1342181376 /* 0x50001000 */
#define DT_N_S_soc_S_dac_50001000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dac_50001000_FOREACH_REG(fn) fn(DT_N_S_soc_S_dac_50001000, 0)
#define DT_N_S_soc_S_dac_50001000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50001000, 0)
#define DT_N_S_soc_S_dac_50001000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_RANGES_NUM 0
#define DT_N_S_soc_S_dac_50001000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dac_50001000_IRQ_NUM 0
#define DT_N_S_soc_S_dac_50001000_IRQ_LEVEL 0
#define DT_N_S_soc_S_dac_50001000_COMPAT_MATCHES_st_stm32_dac 1
#define DT_N_S_soc_S_dac_50001000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dac_50001000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_COMPAT_MODEL_IDX_0 "stm32-dac"
#define DT_N_S_soc_S_dac_50001000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dac_50001000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dac_50001000_P_reg {1342181376 /* 0x50001000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dac_50001000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_reg_IDX_0 1342181376
#define DT_N_S_soc_S_dac_50001000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dac_50001000_P_reg_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_VAL_bits 262144
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dac_50001000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dac_50001000, clocks, 0, bits)
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50001000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dac_50001000, clocks, 0, bits)
#define DT_N_S_soc_S_dac_50001000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dac_50001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50001000, clocks, 0)
#define DT_N_S_soc_S_dac_50001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50001000, clocks, 0)
#define DT_N_S_soc_S_dac_50001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50001000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50001000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_P_clocks_LEN 1
#define DT_N_S_soc_S_dac_50001000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_status "disabled"
#define DT_N_S_soc_S_dac_50001000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_dac_50001000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_dac_50001000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_dac_50001000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_dac_50001000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_dac_50001000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50001000, status, 0)
#define DT_N_S_soc_S_dac_50001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50001000, status, 0)
#define DT_N_S_soc_S_dac_50001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_P_status_LEN 1
#define DT_N_S_soc_S_dac_50001000_P_status_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_compatible {"st,stm32-dac"}
#define DT_N_S_soc_S_dac_50001000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_compatible_IDX_0 "st,stm32-dac"
#define DT_N_S_soc_S_dac_50001000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dac
#define DT_N_S_soc_S_dac_50001000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dac
#define DT_N_S_soc_S_dac_50001000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DAC
#define DT_N_S_soc_S_dac_50001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_50001000, compatible, 0)
#define DT_N_S_soc_S_dac_50001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_50001000, compatible, 0)
#define DT_N_S_soc_S_dac_50001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_50001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_50001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dac_50001000_P_compatible_LEN 1
#define DT_N_S_soc_S_dac_50001000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_dma_coherent 0
#define DT_N_S_soc_S_dac_50001000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dac_50001000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_wakeup_source 0
#define DT_N_S_soc_S_dac_50001000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dac_50001000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dac_50001000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/dma@40020400
 *
 * Node identifier: DT_N_S_soc_S_dma_40020400
 *
 * Binding (compatible = st,stm32-dma-v2):
 *   $ZEPHYR_BASE/dts/bindings/dma/st,stm32-dma-v2.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dma_40020400_PATH "/soc/dma@40020400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dma_40020400_FULL_NAME "dma@40020400"
#define DT_N_S_soc_S_dma_40020400_FULL_NAME_UNQUOTED dma@40020400
#define DT_N_S_soc_S_dma_40020400_FULL_NAME_TOKEN dma_40020400
#define DT_N_S_soc_S_dma_40020400_FULL_NAME_UPPER_TOKEN DMA_40020400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dma_40020400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dma_40020400_CHILD_IDX 39

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dma_40020400_NODELABEL_NUM 1
#define DT_N_S_soc_S_dma_40020400_FOREACH_NODELABEL(fn) fn(dma2)
#define DT_N_S_soc_S_dma_40020400_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma2, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dma_40020400_CHILD_NUM 0
#define DT_N_S_soc_S_dma_40020400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dma_40020400_HASH 6M2mn87tCKiqdKtfbifYbjloijPkEmcQ0zczmKi97Y8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dma_40020400_ORD 60
#define DT_N_S_soc_S_dma_40020400_ORD_STR_SORTABLE 00060

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dma_40020400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dma_40020400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dma_40020400_EXISTS 1
#define DT_N_INST_1_st_stm32_dma_v2 DT_N_S_soc_S_dma_40020400
#define DT_N_NODELABEL_dma2         DT_N_S_soc_S_dma_40020400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dma_40020400_REG_NUM 1
#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_VAL_ADDRESS 1073873920 /* 0x40020400 */
#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dma_40020400_FOREACH_REG(fn) fn(DT_N_S_soc_S_dma_40020400, 0)
#define DT_N_S_soc_S_dma_40020400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, 0)
#define DT_N_S_soc_S_dma_40020400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_RANGES_NUM 0
#define DT_N_S_soc_S_dma_40020400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dma_40020400_IRQ_NUM 6
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_VAL_irq 56
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_VAL_irq 57
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_VAL_irq 58
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_VAL_irq 59
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_VAL_irq 60
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_VAL_irq 97
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020400_IRQ_LEVEL 1
#define DT_N_S_soc_S_dma_40020400_COMPAT_MATCHES_st_stm32_dma_v2 1
#define DT_N_S_soc_S_dma_40020400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dma_40020400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_COMPAT_MODEL_IDX_0 "stm32-dma-v2"
#define DT_N_S_soc_S_dma_40020400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dma_40020400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dma_40020400_P_reg {1073873920 /* 0x40020400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_0 1073873920
#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dma_40020400_P_reg_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts {56 /* 0x38 */, 0 /* 0x0 */, 57 /* 0x39 */, 0 /* 0x0 */, 58 /* 0x3a */, 0 /* 0x0 */, 59 /* 0x3b */, 0 /* 0x0 */, 60 /* 0x3c */, 0 /* 0x0 */, 97 /* 0x61 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_0 56
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_2 57
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_4 58
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_6 59
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_8 60
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_9 0
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_10 97
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_11 0
#define DT_N_S_soc_S_dma_40020400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_st_mem2mem 0
#define DT_N_S_soc_S_dma_40020400_P_st_mem2mem_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_dma_offset 6
#define DT_N_S_soc_S_dma_40020400_P_dma_offset_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_dma_requests 6
#define DT_N_S_soc_S_dma_40020400_P_dma_requests_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_status "disabled"
#define DT_N_S_soc_S_dma_40020400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_dma_40020400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_dma_40020400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_dma_40020400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_dma_40020400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_dma_40020400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020400, status, 0)
#define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, status, 0)
#define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_P_status_LEN 1
#define DT_N_S_soc_S_dma_40020400_P_status_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_compatible {"st,stm32-dma-v2"}
#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0 "st,stm32-dma-v2"
#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v2
#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v2
#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V2
#define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020400, compatible, 0)
#define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, compatible, 0)
#define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_P_compatible_LEN 1
#define DT_N_S_soc_S_dma_40020400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_VAL_bus 72
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_VAL_bits 2
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dma_40020400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dma_40020400, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dma_40020400, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dma_40020400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020400, clocks, 0)
#define DT_N_S_soc_S_dma_40020400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, clocks, 0)
#define DT_N_S_soc_S_dma_40020400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020400_P_clocks_LEN 1
#define DT_N_S_soc_S_dma_40020400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_dma_coherent 0
#define DT_N_S_soc_S_dma_40020400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dma_40020400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_wakeup_source 0
#define DT_N_S_soc_S_dma_40020400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dma_40020400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dma_40020400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/dmamux@40020800
 *
 * Node identifier: DT_N_S_soc_S_dmamux_40020800
 *
 * Binding (compatible = st,stm32-dmamux):
 *   $ZEPHYR_BASE/dts/bindings/dma/st,stm32-dmamux.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dmamux_40020800_PATH "/soc/dmamux@40020800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME "dmamux@40020800"
#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME_UNQUOTED dmamux@40020800
#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME_TOKEN dmamux_40020800
#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME_UPPER_TOKEN DMAMUX_40020800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dmamux_40020800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dmamux_40020800_CHILD_IDX 40

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dmamux_40020800_NODELABEL_NUM 1
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_NODELABEL(fn) fn(dmamux1)
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_NODELABEL_VARGS(fn, ...) fn(dmamux1, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dmamux_40020800_CHILD_NUM 0
#define DT_N_S_soc_S_dmamux_40020800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dmamux_40020800_HASH jGulMrGrDMjffC0jOcX9YAYtoaIaoNYHlAm2EvPJs_w

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dmamux_40020800_ORD 61
#define DT_N_S_soc_S_dmamux_40020800_ORD_STR_SORTABLE 00061

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dmamux_40020800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dmamux_40020800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dmamux_40020800_EXISTS 1
#define DT_N_INST_0_st_stm32_dmamux DT_N_S_soc_S_dmamux_40020800
#define DT_N_NODELABEL_dmamux1      DT_N_S_soc_S_dmamux_40020800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dmamux_40020800_REG_NUM 1
#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_VAL_ADDRESS 1073874944 /* 0x40020800 */
#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_REG(fn) fn(DT_N_S_soc_S_dmamux_40020800, 0)
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, 0)
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dmamux_40020800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_RANGES_NUM 0
#define DT_N_S_soc_S_dmamux_40020800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dmamux_40020800_IRQ_NUM 1
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_VAL_irq 94
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dmamux_40020800_IRQ_LEVEL 1
#define DT_N_S_soc_S_dmamux_40020800_COMPAT_MATCHES_st_stm32_dmamux 1
#define DT_N_S_soc_S_dmamux_40020800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dmamux_40020800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_COMPAT_MODEL_IDX_0 "stm32-dmamux"
#define DT_N_S_soc_S_dmamux_40020800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dmamux_40020800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dmamux_40020800_P_reg {1073874944 /* 0x40020800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_0 1073874944
#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dmamux_40020800_P_reg_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_dma_channels 12
#define DT_N_S_soc_S_dmamux_40020800_P_dma_channels_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_dma_generators 4
#define DT_N_S_soc_S_dmamux_40020800_P_dma_generators_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_dma_requests 111
#define DT_N_S_soc_S_dmamux_40020800_P_dma_requests_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_status "disabled"
#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_40020800, status, 0)
#define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, status, 0)
#define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dmamux_40020800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_P_status_LEN 1
#define DT_N_S_soc_S_dmamux_40020800_P_status_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_compatible {"st,stm32-dmamux"}
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0 "st,stm32-dmamux"
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dmamux
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_STRING_TOKEN st_stm32_dmamux
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMAMUX
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0)
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0)
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_LEN 1
#define DT_N_S_soc_S_dmamux_40020800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_interrupts {94 /* 0x5e */, 0 /* 0x0 */}
#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_0 94
#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_VAL_bus 72
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_VAL_bits 4
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0, bits)
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0, bits)
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0)
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0)
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dmamux_40020800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_LEN 1
#define DT_N_S_soc_S_dmamux_40020800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_dma_coherent 0
#define DT_N_S_soc_S_dmamux_40020800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source 0
#define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@40010400
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_40010400
 *
 * Binding (compatible = st,stm32-exti):
 *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/st,stm32-exti.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_40010400_PATH "/soc/interrupt-controller@40010400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_40010400_FULL_NAME "interrupt-controller@40010400"
#define DT_N_S_soc_S_interrupt_controller_40010400_FULL_NAME_UNQUOTED interrupt-controller@40010400
#define DT_N_S_soc_S_interrupt_controller_40010400_FULL_NAME_TOKEN interrupt_controller_40010400
#define DT_N_S_soc_S_interrupt_controller_40010400_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_40010400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_40010400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_40010400_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_interrupt_controller_40010400_NODELABEL_NUM 1
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_NODELABEL(fn) fn(exti)
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_NODELABEL_VARGS(fn, ...) fn(exti, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_40010400_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_40010400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_interrupt_controller_40010400_HASH e_jpSkD_2HRRVwDpnnAQSjqS4ZdVHIcY8woRSWkf10Q

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_40010400_ORD 62
#define DT_N_S_soc_S_interrupt_controller_40010400_ORD_STR_SORTABLE 00062

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_40010400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_40010400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_40010400_EXISTS 1
#define DT_N_INST_0_st_stm32_exti DT_N_S_soc_S_interrupt_controller_40010400
#define DT_N_NODELABEL_exti       DT_N_S_soc_S_interrupt_controller_40010400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_40010400_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_40010400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_REG_IDX_0_VAL_ADDRESS 1073808384 /* 0x40010400 */
#define DT_N_S_soc_S_interrupt_controller_40010400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_REG(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400, 0)
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40010400, 0)
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_40010400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NUM 7
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_VAL_irq 6
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_VAL_irq 7
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_VAL_irq 8
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_VAL_irq 9
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_VAL_irq 10
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_VAL_irq 23
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_VAL_irq 40
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_VAL_priority 0
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_LEVEL 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line0_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line0_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line0_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line1_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line1_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line1_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line2_tsc_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line2_tsc_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line2_tsc_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line2_tsc_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line2_tsc_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line3_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line3_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line3_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line4_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line4_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line4_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_4_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line5_9_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line5_9_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line5_9_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line5_9_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line5_9_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_5_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line10_15_VAL_irq DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_VAL_irq
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line10_15_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line10_15_VAL_priority DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_VAL_priority
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line10_15_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_IRQ_NAME_line10_15_CONTROLLER DT_N_S_soc_S_interrupt_controller_40010400_IRQ_IDX_6_CONTROLLER
#define DT_N_S_soc_S_interrupt_controller_40010400_COMPAT_MATCHES_st_stm32_exti 1
#define DT_N_S_soc_S_interrupt_controller_40010400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_interrupt_controller_40010400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_COMPAT_MODEL_IDX_0 "stm32-exti"
#define DT_N_S_soc_S_interrupt_controller_40010400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_40010400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_40010400_P_reg {1073808384 /* 0x40010400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_interrupt_controller_40010400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_reg_IDX_0 1073808384
#define DT_N_S_soc_S_interrupt_controller_40010400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_interrupt_controller_40010400_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts {6 /* 0x6 */, 0 /* 0x0 */, 7 /* 0x7 */, 0 /* 0x0 */, 8 /* 0x8 */, 0 /* 0x0 */, 9 /* 0x9 */, 0 /* 0x0 */, 10 /* 0xa */, 0 /* 0x0 */, 23 /* 0x17 */, 0 /* 0x0 */, 40 /* 0x28 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_0 6
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_2 7
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_4 8
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_6 9
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_8 10
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_9 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_10 23
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_11 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_12_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_12 40
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_13_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_IDX_13 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names {"line0", "line1", "line2-TSC", "line3", "line4", "line5-9", "line10-15"}
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_0 "line0"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_0_STRING_UNQUOTED line0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_0_STRING_TOKEN line0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN LINE0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_1 "line1"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_1_STRING_UNQUOTED line1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_1_STRING_TOKEN line1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN LINE1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_2 "line2-TSC"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_2_STRING_UNQUOTED line2-TSC
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_2_STRING_TOKEN line2_TSC
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN LINE2_TSC
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_3 "line3"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_3_STRING_UNQUOTED line3
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_3_STRING_TOKEN line3
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN LINE3
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_4 "line4"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_4_STRING_UNQUOTED line4
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_4_STRING_TOKEN line4
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_4_STRING_UPPER_TOKEN LINE4
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_5 "line5-9"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_5_STRING_UNQUOTED line5-9
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_5_STRING_TOKEN line5_9
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_5_STRING_UPPER_TOKEN LINE5_9
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_6 "line10-15"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_6_STRING_UNQUOTED line10-15
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_6_STRING_TOKEN line10_15
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_IDX_6_STRING_UPPER_TOKEN LINE10_15
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 1) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 2) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 3) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 4) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 5) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 6)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 6)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 6, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, interrupt_names, 6, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_LEN 7
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_num_lines 64
#define DT_N_S_soc_S_interrupt_controller_40010400_P_num_lines_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_num_gpio_lines 16
#define DT_N_S_soc_S_interrupt_controller_40010400_P_num_gpio_lines_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges {0 /* 0x0 */, 1 /* 0x1 */, 1 /* 0x1 */, 1 /* 0x1 */, 2 /* 0x2 */, 1 /* 0x1 */, 3 /* 0x3 */, 1 /* 0x1 */, 4 /* 0x4 */, 1 /* 0x1 */, 5 /* 0x5 */, 5 /* 0x5 */, 10 /* 0xa */, 6 /* 0x6 */}
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_0 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_1 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_2_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_2 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_3_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_3 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_4_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_4 2
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_5_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_5 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_6_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_6 3
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_7_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_7 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_8_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_8 4
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_9_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_9 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_10_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_10 5
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_11_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_11 5
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_12_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_12 10
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_13_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_IDX_13 6
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 0) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 1) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 2) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 3) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 4) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 5) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 6) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 7) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 8) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 9) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 10) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 11) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 12) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 13)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 13)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 13, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, line_ranges, 13, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_LEN 14
#define DT_N_S_soc_S_interrupt_controller_40010400_P_line_ranges_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible {"st,stm32-exti"}
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_IDX_0 "st,stm32-exti"
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-exti
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_IDX_0_STRING_TOKEN st_stm32_exti
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_EXTI
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40010400, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0, bits)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0, bits)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_LEN 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_dma_coherent 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_40010400_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_40010400_P_interrupt_controller_EXISTS 1

/*
 * Devicetree node: /soc/opamp1@40010300
 *
 * Node identifier: DT_N_S_soc_S_opamp1_40010300
 *
 * Binding (compatible = st,stm32g4-opamp):
 *   $ZEPHYR_BASE/dts/bindings/opamp/st,stm32g4-opamp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_opamp1_40010300_PATH "/soc/opamp1@40010300"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_opamp1_40010300_FULL_NAME "opamp1@40010300"
#define DT_N_S_soc_S_opamp1_40010300_FULL_NAME_UNQUOTED opamp1@40010300
#define DT_N_S_soc_S_opamp1_40010300_FULL_NAME_TOKEN opamp1_40010300
#define DT_N_S_soc_S_opamp1_40010300_FULL_NAME_UPPER_TOKEN OPAMP1_40010300

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_opamp1_40010300_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_opamp1_40010300_CHILD_IDX 44

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_opamp1_40010300_NODELABEL_NUM 1
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_NODELABEL(fn) fn(opamp1)
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_NODELABEL_VARGS(fn, ...) fn(opamp1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_opamp1_40010300_CHILD_NUM 0
#define DT_N_S_soc_S_opamp1_40010300_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_opamp1_40010300_HASH aCXNiTfhFhJfAbkt6Jfx73W2ZbtZ_qCtU9RdWmSBUHU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_opamp1_40010300_ORD 63
#define DT_N_S_soc_S_opamp1_40010300_ORD_STR_SORTABLE 00063

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_opamp1_40010300_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_opamp1_40010300_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_opamp1_40010300_EXISTS 1
#define DT_N_INST_0_st_stm32g4_opamp DT_N_S_soc_S_opamp1_40010300
#define DT_N_INST_0_st_stm32_opamp   DT_N_S_soc_S_opamp1_40010300
#define DT_N_NODELABEL_opamp1        DT_N_S_soc_S_opamp1_40010300

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_opamp1_40010300_REG_NUM 1
#define DT_N_S_soc_S_opamp1_40010300_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_REG_IDX_0_VAL_ADDRESS 1073808128 /* 0x40010300 */
#define DT_N_S_soc_S_opamp1_40010300_REG_IDX_0_VAL_SIZE 24 /* 0x18 */
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_REG(fn) fn(DT_N_S_soc_S_opamp1_40010300, 0)
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, 0)
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_RANGES_NUM 0
#define DT_N_S_soc_S_opamp1_40010300_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_opamp1_40010300_IRQ_NUM 0
#define DT_N_S_soc_S_opamp1_40010300_IRQ_LEVEL 0
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_MATCHES_st_stm32g4_opamp 1
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_MODEL_IDX_0 "stm32g4-opamp"
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_MATCHES_st_stm32_opamp 1
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_COMPAT_MODEL_IDX_1 "stm32-opamp"
#define DT_N_S_soc_S_opamp1_40010300_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_opamp1_40010300_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode "NORMAL"
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_STRING_UNQUOTED NORMAL
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_STRING_TOKEN NORMAL
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_STRING_UPPER_TOKEN NORMAL
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_IDX_0 "NORMAL"
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_IDX_0_ENUM_VAL_normal_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_ENUM_VAL_normal_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, st_power_mode, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, st_power_mode, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, st_power_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, st_power_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_LEN 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_power_mode_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_lock_enable 0
#define DT_N_S_soc_S_opamp1_40010300_P_st_lock_enable_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_enable_self_calibration 0
#define DT_N_S_soc_S_opamp1_40010300_P_st_enable_self_calibration_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering "NONE"
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_STRING_TOKEN NONE
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_IDX_0 "NONE"
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, st_inm_filtering, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, st_inm_filtering, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, st_inm_filtering, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, st_inm_filtering, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_LEN 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inm_filtering_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode "DISABLE"
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_STRING_UNQUOTED DISABLE
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_STRING_TOKEN DISABLE
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_STRING_UPPER_TOKEN DISABLE
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_IDX_0 "DISABLE"
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_IDX_0_ENUM_VAL_disable_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_ENUM_VAL_disable_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, st_inputs_mux_mode, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, st_inputs_mux_mode, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, st_inputs_mux_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, st_inputs_mux_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_LEN 1
#define DT_N_S_soc_S_opamp1_40010300_P_st_inputs_mux_mode_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_reg {1073808128 /* 0x40010300 */, 24 /* 0x18 */}
#define DT_N_S_soc_S_opamp1_40010300_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_reg_IDX_0 1073808128
#define DT_N_S_soc_S_opamp1_40010300_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_reg_IDX_1 24
#define DT_N_S_soc_S_opamp1_40010300_P_reg_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0, bus) \
	fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0, bits)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0, bits)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_NAME "opampx"
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_IDX 0
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_opamp1_40010300, clocks, opampx, bus) \
	fn(DT_N_S_soc_S_opamp1_40010300, clocks, opampx, bits)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, clocks, opampx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, clocks, opampx, bits)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_NUM_CELLS 2
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_VAL_bus DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_VAL_bits DT_N_S_soc_S_opamp1_40010300_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_NAME_opampx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_LEN 1
#define DT_N_S_soc_S_opamp1_40010300_P_clocks_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names {"opampx"}
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_IDX_0 "opampx"
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_IDX_0_STRING_UNQUOTED opampx
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_IDX_0_STRING_TOKEN opampx
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_IDX_0_STRING_UPPER_TOKEN OPAMPX
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, clock_names, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, clock_names, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_LEN 1
#define DT_N_S_soc_S_opamp1_40010300_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain {"OPAMP_GAIN_1", "OPAMP_GAIN_2", "OPAMP_GAIN_3", "OPAMP_GAIN_4", "OPAMP_GAIN_7", "OPAMP_GAIN_8", "OPAMP_GAIN_15", "OPAMP_GAIN_16", "OPAMP_GAIN_31", "OPAMP_GAIN_32", "OPAMP_GAIN_63", "OPAMP_GAIN_64"}
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1_ENUM_IDX 4
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2_ENUM_IDX 6
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3_ENUM_IDX 7
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4_ENUM_IDX 9
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5_ENUM_IDX 10
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6_ENUM_IDX 11
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7_ENUM_IDX 12
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8_ENUM_IDX 13
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9_ENUM_IDX 14
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10_ENUM_IDX 16
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11_ENUM_IDX 17
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0_ENUM_VAL_opamp_gain_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1_ENUM_VAL_opamp_gain_2_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_2_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2_ENUM_VAL_opamp_gain_3_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_3_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3_ENUM_VAL_opamp_gain_4_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_4_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4_ENUM_VAL_opamp_gain_7_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_7_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5_ENUM_VAL_opamp_gain_8_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_8_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6_ENUM_VAL_opamp_gain_15_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_15_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7_ENUM_VAL_opamp_gain_16_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_16_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8_ENUM_VAL_opamp_gain_31_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_31_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9_ENUM_VAL_opamp_gain_32_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_32_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10_ENUM_VAL_opamp_gain_63_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_63_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11_ENUM_VAL_opamp_gain_64_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_ENUM_VAL_opamp_gain_64_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0 "OPAMP_GAIN_1"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0_STRING_UNQUOTED OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0_STRING_TOKEN OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_0_STRING_UPPER_TOKEN OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1 "OPAMP_GAIN_2"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1_STRING_UNQUOTED OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1_STRING_TOKEN OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_1_STRING_UPPER_TOKEN OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2 "OPAMP_GAIN_3"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2_STRING_UNQUOTED OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2_STRING_TOKEN OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_2_STRING_UPPER_TOKEN OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3 "OPAMP_GAIN_4"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3_STRING_UNQUOTED OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3_STRING_TOKEN OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_3_STRING_UPPER_TOKEN OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4 "OPAMP_GAIN_7"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4_STRING_UNQUOTED OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4_STRING_TOKEN OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_4_STRING_UPPER_TOKEN OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5 "OPAMP_GAIN_8"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5_STRING_UNQUOTED OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5_STRING_TOKEN OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_5_STRING_UPPER_TOKEN OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6 "OPAMP_GAIN_15"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6_STRING_UNQUOTED OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6_STRING_TOKEN OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_6_STRING_UPPER_TOKEN OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7 "OPAMP_GAIN_16"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7_STRING_UNQUOTED OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7_STRING_TOKEN OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_7_STRING_UPPER_TOKEN OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8 "OPAMP_GAIN_31"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8_STRING_UNQUOTED OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8_STRING_TOKEN OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_8_STRING_UPPER_TOKEN OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9 "OPAMP_GAIN_32"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9_STRING_UNQUOTED OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9_STRING_TOKEN OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_9_STRING_UPPER_TOKEN OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10 "OPAMP_GAIN_63"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10_STRING_UNQUOTED OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10_STRING_TOKEN OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_10_STRING_UPPER_TOKEN OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11 "OPAMP_GAIN_64"
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11_STRING_UNQUOTED OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11_STRING_TOKEN OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_IDX_11_STRING_UPPER_TOKEN OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 0) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 1) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 2) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 3) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 4) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 5) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 6) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 7) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 8) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 9) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 10) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 11)
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 11)
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 11, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, programmable_gain, 11, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_LEN 12
#define DT_N_S_soc_S_opamp1_40010300_P_programmable_gain_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_status "disabled"
#define DT_N_S_soc_S_opamp1_40010300_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_opamp1_40010300_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_opamp1_40010300_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_opamp1_40010300_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_opamp1_40010300_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_opamp1_40010300_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, status, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, status, 0)
#define DT_N_S_soc_S_opamp1_40010300_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_status_LEN 1
#define DT_N_S_soc_S_opamp1_40010300_P_status_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_compatible {"st,stm32g4-opamp", "st,stm32-opamp"}
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_0 "st,stm32g4-opamp"
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g4-opamp
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_0_STRING_TOKEN st_stm32g4_opamp
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G4_OPAMP
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_1 "st,stm32-opamp"
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-opamp
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_1_STRING_TOKEN st_stm32_opamp
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_OPAMP
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp1_40010300, compatible, 0) \
	fn(DT_N_S_soc_S_opamp1_40010300, compatible, 1)
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp1_40010300, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, compatible, 1)
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp1_40010300, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp1_40010300, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp1_40010300, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp1_40010300, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_LEN 2
#define DT_N_S_soc_S_opamp1_40010300_P_compatible_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_dma_coherent 0
#define DT_N_S_soc_S_opamp1_40010300_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_opamp1_40010300_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_wakeup_source 0
#define DT_N_S_soc_S_opamp1_40010300_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_opamp1_40010300_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_opamp1_40010300_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/opamp2@40010304
 *
 * Node identifier: DT_N_S_soc_S_opamp2_40010304
 *
 * Binding (compatible = st,stm32g4-opamp):
 *   $ZEPHYR_BASE/dts/bindings/opamp/st,stm32g4-opamp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_opamp2_40010304_PATH "/soc/opamp2@40010304"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_opamp2_40010304_FULL_NAME "opamp2@40010304"
#define DT_N_S_soc_S_opamp2_40010304_FULL_NAME_UNQUOTED opamp2@40010304
#define DT_N_S_soc_S_opamp2_40010304_FULL_NAME_TOKEN opamp2_40010304
#define DT_N_S_soc_S_opamp2_40010304_FULL_NAME_UPPER_TOKEN OPAMP2_40010304

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_opamp2_40010304_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_opamp2_40010304_CHILD_IDX 45

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_opamp2_40010304_NODELABEL_NUM 1
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_NODELABEL(fn) fn(opamp2)
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_NODELABEL_VARGS(fn, ...) fn(opamp2, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_opamp2_40010304_CHILD_NUM 0
#define DT_N_S_soc_S_opamp2_40010304_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_opamp2_40010304_HASH ckim8RZj5_Q3nSyk6mDYnK5krFNwlh6M5jrnAEWaPiw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_opamp2_40010304_ORD 64
#define DT_N_S_soc_S_opamp2_40010304_ORD_STR_SORTABLE 00064

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_opamp2_40010304_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_opamp2_40010304_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_opamp2_40010304_EXISTS 1
#define DT_N_INST_1_st_stm32g4_opamp DT_N_S_soc_S_opamp2_40010304
#define DT_N_INST_1_st_stm32_opamp   DT_N_S_soc_S_opamp2_40010304
#define DT_N_NODELABEL_opamp2        DT_N_S_soc_S_opamp2_40010304

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_opamp2_40010304_REG_NUM 1
#define DT_N_S_soc_S_opamp2_40010304_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_REG_IDX_0_VAL_ADDRESS 1073808132 /* 0x40010304 */
#define DT_N_S_soc_S_opamp2_40010304_REG_IDX_0_VAL_SIZE 24 /* 0x18 */
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_REG(fn) fn(DT_N_S_soc_S_opamp2_40010304, 0)
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, 0)
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_RANGES_NUM 0
#define DT_N_S_soc_S_opamp2_40010304_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_opamp2_40010304_IRQ_NUM 0
#define DT_N_S_soc_S_opamp2_40010304_IRQ_LEVEL 0
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_MATCHES_st_stm32g4_opamp 1
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_MODEL_IDX_0 "stm32g4-opamp"
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_MATCHES_st_stm32_opamp 1
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_COMPAT_MODEL_IDX_1 "stm32-opamp"
#define DT_N_S_soc_S_opamp2_40010304_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_opamp2_40010304_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode "NORMAL"
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_STRING_UNQUOTED NORMAL
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_STRING_TOKEN NORMAL
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_STRING_UPPER_TOKEN NORMAL
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_IDX_0 "NORMAL"
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_IDX_0_ENUM_VAL_normal_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_ENUM_VAL_normal_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, st_power_mode, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, st_power_mode, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, st_power_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, st_power_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_LEN 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_power_mode_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_lock_enable 0
#define DT_N_S_soc_S_opamp2_40010304_P_st_lock_enable_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_enable_self_calibration 0
#define DT_N_S_soc_S_opamp2_40010304_P_st_enable_self_calibration_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering "NONE"
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_STRING_TOKEN NONE
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_IDX_0 "NONE"
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, st_inm_filtering, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, st_inm_filtering, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, st_inm_filtering, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, st_inm_filtering, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_LEN 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inm_filtering_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode "DISABLE"
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_STRING_UNQUOTED DISABLE
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_STRING_TOKEN DISABLE
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_STRING_UPPER_TOKEN DISABLE
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_IDX_0 "DISABLE"
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_IDX_0_ENUM_VAL_disable_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_ENUM_VAL_disable_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, st_inputs_mux_mode, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, st_inputs_mux_mode, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, st_inputs_mux_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, st_inputs_mux_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_LEN 1
#define DT_N_S_soc_S_opamp2_40010304_P_st_inputs_mux_mode_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_reg {1073808132 /* 0x40010304 */, 24 /* 0x18 */}
#define DT_N_S_soc_S_opamp2_40010304_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_reg_IDX_0 1073808132
#define DT_N_S_soc_S_opamp2_40010304_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_reg_IDX_1 24
#define DT_N_S_soc_S_opamp2_40010304_P_reg_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0, bus) \
	fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0, bits)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0, bits)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_NAME "opampx"
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_IDX 0
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_opamp2_40010304, clocks, opampx, bus) \
	fn(DT_N_S_soc_S_opamp2_40010304, clocks, opampx, bits)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, clocks, opampx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, clocks, opampx, bits)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_NUM_CELLS 2
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_VAL_bus DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_VAL_bits DT_N_S_soc_S_opamp2_40010304_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_NAME_opampx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_LEN 1
#define DT_N_S_soc_S_opamp2_40010304_P_clocks_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names {"opampx"}
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_IDX_0 "opampx"
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_IDX_0_STRING_UNQUOTED opampx
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_IDX_0_STRING_TOKEN opampx
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_IDX_0_STRING_UPPER_TOKEN OPAMPX
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, clock_names, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, clock_names, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_LEN 1
#define DT_N_S_soc_S_opamp2_40010304_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain {"OPAMP_GAIN_1", "OPAMP_GAIN_2", "OPAMP_GAIN_3", "OPAMP_GAIN_4", "OPAMP_GAIN_7", "OPAMP_GAIN_8", "OPAMP_GAIN_15", "OPAMP_GAIN_16", "OPAMP_GAIN_31", "OPAMP_GAIN_32", "OPAMP_GAIN_63", "OPAMP_GAIN_64"}
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1_ENUM_IDX 4
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2_ENUM_IDX 6
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3_ENUM_IDX 7
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4_ENUM_IDX 9
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5_ENUM_IDX 10
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6_ENUM_IDX 11
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7_ENUM_IDX 12
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8_ENUM_IDX 13
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9_ENUM_IDX 14
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10_ENUM_IDX 16
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11_ENUM_IDX 17
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0_ENUM_VAL_opamp_gain_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1_ENUM_VAL_opamp_gain_2_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_2_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2_ENUM_VAL_opamp_gain_3_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_3_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3_ENUM_VAL_opamp_gain_4_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_4_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4_ENUM_VAL_opamp_gain_7_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_7_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5_ENUM_VAL_opamp_gain_8_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_8_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6_ENUM_VAL_opamp_gain_15_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_15_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7_ENUM_VAL_opamp_gain_16_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_16_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8_ENUM_VAL_opamp_gain_31_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_31_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9_ENUM_VAL_opamp_gain_32_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_32_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10_ENUM_VAL_opamp_gain_63_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_63_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11_ENUM_VAL_opamp_gain_64_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_ENUM_VAL_opamp_gain_64_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0 "OPAMP_GAIN_1"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0_STRING_UNQUOTED OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0_STRING_TOKEN OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_0_STRING_UPPER_TOKEN OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1 "OPAMP_GAIN_2"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1_STRING_UNQUOTED OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1_STRING_TOKEN OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_1_STRING_UPPER_TOKEN OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2 "OPAMP_GAIN_3"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2_STRING_UNQUOTED OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2_STRING_TOKEN OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_2_STRING_UPPER_TOKEN OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3 "OPAMP_GAIN_4"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3_STRING_UNQUOTED OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3_STRING_TOKEN OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_3_STRING_UPPER_TOKEN OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4 "OPAMP_GAIN_7"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4_STRING_UNQUOTED OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4_STRING_TOKEN OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_4_STRING_UPPER_TOKEN OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5 "OPAMP_GAIN_8"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5_STRING_UNQUOTED OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5_STRING_TOKEN OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_5_STRING_UPPER_TOKEN OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6 "OPAMP_GAIN_15"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6_STRING_UNQUOTED OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6_STRING_TOKEN OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_6_STRING_UPPER_TOKEN OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7 "OPAMP_GAIN_16"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7_STRING_UNQUOTED OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7_STRING_TOKEN OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_7_STRING_UPPER_TOKEN OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8 "OPAMP_GAIN_31"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8_STRING_UNQUOTED OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8_STRING_TOKEN OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_8_STRING_UPPER_TOKEN OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9 "OPAMP_GAIN_32"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9_STRING_UNQUOTED OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9_STRING_TOKEN OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_9_STRING_UPPER_TOKEN OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10 "OPAMP_GAIN_63"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10_STRING_UNQUOTED OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10_STRING_TOKEN OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_10_STRING_UPPER_TOKEN OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11 "OPAMP_GAIN_64"
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11_STRING_UNQUOTED OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11_STRING_TOKEN OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_IDX_11_STRING_UPPER_TOKEN OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 0) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 1) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 2) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 3) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 4) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 5) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 6) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 7) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 8) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 9) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 10) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 11)
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 11)
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 11, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, programmable_gain, 11, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_LEN 12
#define DT_N_S_soc_S_opamp2_40010304_P_programmable_gain_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_status "disabled"
#define DT_N_S_soc_S_opamp2_40010304_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_opamp2_40010304_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_opamp2_40010304_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_opamp2_40010304_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_opamp2_40010304_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_opamp2_40010304_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, status, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, status, 0)
#define DT_N_S_soc_S_opamp2_40010304_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_status_LEN 1
#define DT_N_S_soc_S_opamp2_40010304_P_status_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_compatible {"st,stm32g4-opamp", "st,stm32-opamp"}
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_0 "st,stm32g4-opamp"
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g4-opamp
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_0_STRING_TOKEN st_stm32g4_opamp
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G4_OPAMP
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_1 "st,stm32-opamp"
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-opamp
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_1_STRING_TOKEN st_stm32_opamp
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_OPAMP
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp2_40010304, compatible, 0) \
	fn(DT_N_S_soc_S_opamp2_40010304, compatible, 1)
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp2_40010304, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, compatible, 1)
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp2_40010304, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp2_40010304, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp2_40010304, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp2_40010304, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_LEN 2
#define DT_N_S_soc_S_opamp2_40010304_P_compatible_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_dma_coherent 0
#define DT_N_S_soc_S_opamp2_40010304_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_opamp2_40010304_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_wakeup_source 0
#define DT_N_S_soc_S_opamp2_40010304_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_opamp2_40010304_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_opamp2_40010304_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/opamp3@40010308
 *
 * Node identifier: DT_N_S_soc_S_opamp3_40010308
 *
 * Binding (compatible = st,stm32g4-opamp):
 *   $ZEPHYR_BASE/dts/bindings/opamp/st,stm32g4-opamp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_opamp3_40010308_PATH "/soc/opamp3@40010308"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_opamp3_40010308_FULL_NAME "opamp3@40010308"
#define DT_N_S_soc_S_opamp3_40010308_FULL_NAME_UNQUOTED opamp3@40010308
#define DT_N_S_soc_S_opamp3_40010308_FULL_NAME_TOKEN opamp3_40010308
#define DT_N_S_soc_S_opamp3_40010308_FULL_NAME_UPPER_TOKEN OPAMP3_40010308

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_opamp3_40010308_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_opamp3_40010308_CHILD_IDX 46

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_opamp3_40010308_NODELABEL_NUM 1
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_NODELABEL(fn) fn(opamp3)
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_NODELABEL_VARGS(fn, ...) fn(opamp3, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_opamp3_40010308_CHILD_NUM 0
#define DT_N_S_soc_S_opamp3_40010308_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_opamp3_40010308_HASH ipHNN3tjmXTPhEKG4Q1KM0oSK0qlxT8pZq_uY3Ty_3o

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_opamp3_40010308_ORD 65
#define DT_N_S_soc_S_opamp3_40010308_ORD_STR_SORTABLE 00065

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_opamp3_40010308_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_opamp3_40010308_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_opamp3_40010308_EXISTS 1
#define DT_N_INST_2_st_stm32g4_opamp DT_N_S_soc_S_opamp3_40010308
#define DT_N_INST_2_st_stm32_opamp   DT_N_S_soc_S_opamp3_40010308
#define DT_N_NODELABEL_opamp3        DT_N_S_soc_S_opamp3_40010308

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_opamp3_40010308_REG_NUM 1
#define DT_N_S_soc_S_opamp3_40010308_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_REG_IDX_0_VAL_ADDRESS 1073808136 /* 0x40010308 */
#define DT_N_S_soc_S_opamp3_40010308_REG_IDX_0_VAL_SIZE 24 /* 0x18 */
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_REG(fn) fn(DT_N_S_soc_S_opamp3_40010308, 0)
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, 0)
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_RANGES_NUM 0
#define DT_N_S_soc_S_opamp3_40010308_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_opamp3_40010308_IRQ_NUM 0
#define DT_N_S_soc_S_opamp3_40010308_IRQ_LEVEL 0
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_MATCHES_st_stm32g4_opamp 1
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_MODEL_IDX_0 "stm32g4-opamp"
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_MATCHES_st_stm32_opamp 1
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_COMPAT_MODEL_IDX_1 "stm32-opamp"
#define DT_N_S_soc_S_opamp3_40010308_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_opamp3_40010308_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode "NORMAL"
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_STRING_UNQUOTED NORMAL
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_STRING_TOKEN NORMAL
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_STRING_UPPER_TOKEN NORMAL
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_IDX_0 "NORMAL"
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_IDX_0_ENUM_VAL_normal_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_ENUM_VAL_normal_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, st_power_mode, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, st_power_mode, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, st_power_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, st_power_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_LEN 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_power_mode_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_lock_enable 0
#define DT_N_S_soc_S_opamp3_40010308_P_st_lock_enable_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_enable_self_calibration 0
#define DT_N_S_soc_S_opamp3_40010308_P_st_enable_self_calibration_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering "NONE"
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_STRING_UNQUOTED NONE
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_STRING_TOKEN NONE
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_IDX_0 "NONE"
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, st_inm_filtering, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, st_inm_filtering, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, st_inm_filtering, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, st_inm_filtering, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_LEN 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inm_filtering_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode "DISABLE"
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_STRING_UNQUOTED DISABLE
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_STRING_TOKEN DISABLE
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_STRING_UPPER_TOKEN DISABLE
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_IDX_0 "DISABLE"
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_IDX_0_ENUM_VAL_disable_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_ENUM_VAL_disable_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, st_inputs_mux_mode, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, st_inputs_mux_mode, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, st_inputs_mux_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, st_inputs_mux_mode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_LEN 1
#define DT_N_S_soc_S_opamp3_40010308_P_st_inputs_mux_mode_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_reg {1073808136 /* 0x40010308 */, 24 /* 0x18 */}
#define DT_N_S_soc_S_opamp3_40010308_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_reg_IDX_0 1073808136
#define DT_N_S_soc_S_opamp3_40010308_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_reg_IDX_1 24
#define DT_N_S_soc_S_opamp3_40010308_P_reg_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0, bus) \
	fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0, bits)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0, bits)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_NAME "opampx"
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_IDX 0
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_opamp3_40010308, clocks, opampx, bus) \
	fn(DT_N_S_soc_S_opamp3_40010308, clocks, opampx, bits)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, clocks, opampx, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, clocks, opampx, bits)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_NUM_CELLS 2
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_VAL_bus DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_VAL_bus
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_VAL_bits DT_N_S_soc_S_opamp3_40010308_P_clocks_IDX_0_VAL_bits
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_NAME_opampx_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_LEN 1
#define DT_N_S_soc_S_opamp3_40010308_P_clocks_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names {"opampx"}
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_IDX_0 "opampx"
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_IDX_0_STRING_UNQUOTED opampx
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_IDX_0_STRING_TOKEN opampx
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_IDX_0_STRING_UPPER_TOKEN OPAMPX
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, clock_names, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, clock_names, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, clock_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_LEN 1
#define DT_N_S_soc_S_opamp3_40010308_P_clock_names_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain {"OPAMP_GAIN_1", "OPAMP_GAIN_2", "OPAMP_GAIN_3", "OPAMP_GAIN_4", "OPAMP_GAIN_7", "OPAMP_GAIN_8", "OPAMP_GAIN_15", "OPAMP_GAIN_16", "OPAMP_GAIN_31", "OPAMP_GAIN_32", "OPAMP_GAIN_63", "OPAMP_GAIN_64"}
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0_ENUM_IDX 2
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1_ENUM_IDX 4
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2_ENUM_IDX 6
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3_ENUM_IDX 7
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4_ENUM_IDX 9
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5_ENUM_IDX 10
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6_ENUM_IDX 11
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7_ENUM_IDX 12
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8_ENUM_IDX 13
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9_ENUM_IDX 14
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10_ENUM_IDX 16
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11_ENUM_IDX 17
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0_ENUM_VAL_opamp_gain_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1_ENUM_VAL_opamp_gain_2_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_2_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2_ENUM_VAL_opamp_gain_3_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_3_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3_ENUM_VAL_opamp_gain_4_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_4_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4_ENUM_VAL_opamp_gain_7_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_7_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5_ENUM_VAL_opamp_gain_8_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_8_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6_ENUM_VAL_opamp_gain_15_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_15_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7_ENUM_VAL_opamp_gain_16_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_16_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8_ENUM_VAL_opamp_gain_31_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_31_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9_ENUM_VAL_opamp_gain_32_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_32_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10_ENUM_VAL_opamp_gain_63_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_63_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11_ENUM_VAL_opamp_gain_64_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_ENUM_VAL_opamp_gain_64_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0 "OPAMP_GAIN_1"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0_STRING_UNQUOTED OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0_STRING_TOKEN OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_0_STRING_UPPER_TOKEN OPAMP_GAIN_1
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1 "OPAMP_GAIN_2"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1_STRING_UNQUOTED OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1_STRING_TOKEN OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_1_STRING_UPPER_TOKEN OPAMP_GAIN_2
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2 "OPAMP_GAIN_3"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2_STRING_UNQUOTED OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2_STRING_TOKEN OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_2_STRING_UPPER_TOKEN OPAMP_GAIN_3
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3 "OPAMP_GAIN_4"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3_STRING_UNQUOTED OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3_STRING_TOKEN OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_3_STRING_UPPER_TOKEN OPAMP_GAIN_4
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4 "OPAMP_GAIN_7"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4_STRING_UNQUOTED OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4_STRING_TOKEN OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_4_STRING_UPPER_TOKEN OPAMP_GAIN_7
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5 "OPAMP_GAIN_8"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5_STRING_UNQUOTED OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5_STRING_TOKEN OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_5_STRING_UPPER_TOKEN OPAMP_GAIN_8
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6 "OPAMP_GAIN_15"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6_STRING_UNQUOTED OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6_STRING_TOKEN OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_6_STRING_UPPER_TOKEN OPAMP_GAIN_15
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7 "OPAMP_GAIN_16"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7_STRING_UNQUOTED OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7_STRING_TOKEN OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_7_STRING_UPPER_TOKEN OPAMP_GAIN_16
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8 "OPAMP_GAIN_31"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8_STRING_UNQUOTED OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8_STRING_TOKEN OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_8_STRING_UPPER_TOKEN OPAMP_GAIN_31
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9 "OPAMP_GAIN_32"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9_STRING_UNQUOTED OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9_STRING_TOKEN OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_9_STRING_UPPER_TOKEN OPAMP_GAIN_32
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10 "OPAMP_GAIN_63"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10_STRING_UNQUOTED OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10_STRING_TOKEN OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_10_STRING_UPPER_TOKEN OPAMP_GAIN_63
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11 "OPAMP_GAIN_64"
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11_STRING_UNQUOTED OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11_STRING_TOKEN OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_IDX_11_STRING_UPPER_TOKEN OPAMP_GAIN_64
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 0) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 1) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 2) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 3) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 4) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 5) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 6) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 7) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 8) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 9) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 10) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 11)
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 11)
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 11, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, programmable_gain, 11, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_LEN 12
#define DT_N_S_soc_S_opamp3_40010308_P_programmable_gain_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_status "disabled"
#define DT_N_S_soc_S_opamp3_40010308_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_opamp3_40010308_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_opamp3_40010308_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_opamp3_40010308_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_opamp3_40010308_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_opamp3_40010308_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, status, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, status, 0)
#define DT_N_S_soc_S_opamp3_40010308_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_status_LEN 1
#define DT_N_S_soc_S_opamp3_40010308_P_status_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_compatible {"st,stm32g4-opamp", "st,stm32-opamp"}
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_0 "st,stm32g4-opamp"
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_0_STRING_UNQUOTED st,stm32g4-opamp
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_0_STRING_TOKEN st_stm32g4_opamp
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32G4_OPAMP
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_1 "st,stm32-opamp"
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-opamp
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_1_STRING_TOKEN st_stm32_opamp
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_OPAMP
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_opamp3_40010308, compatible, 0) \
	fn(DT_N_S_soc_S_opamp3_40010308, compatible, 1)
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_opamp3_40010308, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, compatible, 1)
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_opamp3_40010308, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_opamp3_40010308, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_opamp3_40010308, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_opamp3_40010308, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_LEN 2
#define DT_N_S_soc_S_opamp3_40010308_P_compatible_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_dma_coherent 0
#define DT_N_S_soc_S_opamp3_40010308_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_opamp3_40010308_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_wakeup_source 0
#define DT_N_S_soc_S_opamp3_40010308_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_opamp3_40010308_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_opamp3_40010308_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rng@50060800
 *
 * Node identifier: DT_N_S_soc_S_rng_50060800
 *
 * Binding (compatible = st,stm32-rng):
 *   $ZEPHYR_BASE/dts/bindings/rng/st,stm32-rng.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rng_50060800_PATH "/soc/rng@50060800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rng_50060800_FULL_NAME "rng@50060800"
#define DT_N_S_soc_S_rng_50060800_FULL_NAME_UNQUOTED rng@50060800
#define DT_N_S_soc_S_rng_50060800_FULL_NAME_TOKEN rng_50060800
#define DT_N_S_soc_S_rng_50060800_FULL_NAME_UPPER_TOKEN RNG_50060800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rng_50060800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rng_50060800_CHILD_IDX 36

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rng_50060800_NODELABEL_NUM 1
#define DT_N_S_soc_S_rng_50060800_FOREACH_NODELABEL(fn) fn(rng)
#define DT_N_S_soc_S_rng_50060800_FOREACH_NODELABEL_VARGS(fn, ...) fn(rng, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rng_50060800_CHILD_NUM 0
#define DT_N_S_soc_S_rng_50060800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rng_50060800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rng_50060800_HASH 8eafQpG6YwQpjan2edsqJHU8l7DaDSiLzDM6EGAP_Uc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rng_50060800_ORD 66
#define DT_N_S_soc_S_rng_50060800_ORD_STR_SORTABLE 00066

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rng_50060800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rng_50060800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rng_50060800_EXISTS 1
#define DT_N_INST_0_st_stm32_rng DT_N_S_soc_S_rng_50060800
#define DT_N_NODELABEL_rng       DT_N_S_soc_S_rng_50060800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rng_50060800_REG_NUM 1
#define DT_N_S_soc_S_rng_50060800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_REG_IDX_0_VAL_ADDRESS 1342572544 /* 0x50060800 */
#define DT_N_S_soc_S_rng_50060800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG(fn) fn(DT_N_S_soc_S_rng_50060800, 0)
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, 0)
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_RANGES_NUM 0
#define DT_N_S_soc_S_rng_50060800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rng_50060800_IRQ_NUM 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_irq 90
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rng_50060800_IRQ_LEVEL 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_MATCHES_st_stm32_rng 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rng_50060800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_COMPAT_MODEL_IDX_0 "stm32-rng"
#define DT_N_S_soc_S_rng_50060800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rng_50060800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rng_50060800_P_reg {1342572544 /* 0x50060800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_0 1342572544
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_rng_50060800_P_reg_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bits 67108864
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bits)
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 0, bits)
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_VAL_bus 5
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_VAL_bits 3801224
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rng_50060800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 1, bits)
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 1, bits)
#define DT_N_S_soc_S_rng_50060800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_50060800, clocks, 0) \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 1)
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 1)
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rng_50060800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_clocks_LEN 2
#define DT_N_S_soc_S_rng_50060800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status "okay"
#define DT_N_S_soc_S_rng_50060800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_rng_50060800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_rng_50060800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rng_50060800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_50060800, status, 0)
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, status, 0)
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_status_LEN 1
#define DT_N_S_soc_S_rng_50060800_P_status_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_compatible {"st,stm32-rng"}
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0 "st,stm32-rng"
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rng
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_STRING_TOKEN st_stm32_rng
#define DT_N_S_soc_S_rng_50060800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RNG
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_50060800, compatible, 0)
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_50060800, compatible, 0)
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_50060800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_50060800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rng_50060800_P_compatible_LEN 1
#define DT_N_S_soc_S_rng_50060800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_interrupts {90 /* 0x5a */, 0 /* 0x0 */}
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_0 90
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_rng_50060800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_dma_coherent 0
#define DT_N_S_soc_S_rng_50060800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rng_50060800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_wakeup_source 0
#define DT_N_S_soc_S_rng_50060800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rng_50060800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rng_50060800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rtc@40002800
 *
 * Node identifier: DT_N_S_soc_S_rtc_40002800
 *
 * Binding (compatible = st,stm32-rtc):
 *   $ZEPHYR_BASE/dts/bindings/rtc/st,stm32-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_40002800_PATH "/soc/rtc@40002800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME "rtc@40002800"
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME_UNQUOTED rtc@40002800
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME_TOKEN rtc_40002800
#define DT_N_S_soc_S_rtc_40002800_FULL_NAME_UPPER_TOKEN RTC_40002800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_40002800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_40002800_CHILD_IDX 35

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rtc_40002800_NODELABEL_NUM 1
#define DT_N_S_soc_S_rtc_40002800_FOREACH_NODELABEL(fn) fn(rtc)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_40002800_CHILD_NUM 0
#define DT_N_S_soc_S_rtc_40002800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40002800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rtc_40002800_HASH gMDUpS7Ndbl4XKI6XlHTk7n7PIqWK98QhTUf_xffseI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_40002800_ORD 67
#define DT_N_S_soc_S_rtc_40002800_ORD_STR_SORTABLE 00067

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_40002800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_40002800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_40002800_EXISTS 1
#define DT_N_INST_0_st_stm32_rtc DT_N_S_soc_S_rtc_40002800
#define DT_N_NODELABEL_rtc       DT_N_S_soc_S_rtc_40002800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_40002800_REG_NUM 1
#define DT_N_S_soc_S_rtc_40002800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_REG_IDX_0_VAL_ADDRESS 1073752064 /* 0x40002800 */
#define DT_N_S_soc_S_rtc_40002800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG(fn) fn(DT_N_S_soc_S_rtc_40002800, 0)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, 0)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_40002800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_40002800_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_irq 41
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rtc_40002800_IRQ_LEVEL 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_MATCHES_st_stm32_rtc 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_rtc_40002800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_COMPAT_MODEL_IDX_0 "stm32-rtc"
#define DT_N_S_soc_S_rtc_40002800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_40002800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_40002800_P_reg {1073752064 /* 0x40002800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_0 1073752064
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_rtc_40002800_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_alarms_count 2
#define DT_N_S_soc_S_rtc_40002800_P_alarms_count_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_alrm_exti_line 17
#define DT_N_S_soc_S_rtc_40002800_P_alrm_exti_line_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_interrupts {41 /* 0x29 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_0 41
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_rtc_40002800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_prescaler 32768
#define DT_N_S_soc_S_rtc_40002800_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status "okay"
#define DT_N_S_soc_S_rtc_40002800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_rtc_40002800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_rtc_40002800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_rtc_40002800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800, status, 0)
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, status, 0)
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_status_LEN 1
#define DT_N_S_soc_S_rtc_40002800_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_compatible {"st,stm32-rtc"}
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0 "st,stm32-rtc"
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rtc
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_STRING_TOKEN st_stm32_rtc
#define DT_N_S_soc_S_rtc_40002800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RTC
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_40002800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bits 1024
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bus 3
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bits 36176016
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, bits)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40002800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_rtc_40002800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40002800_P_clocks_LEN 2
#define DT_N_S_soc_S_rtc_40002800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_dma_coherent 0
#define DT_N_S_soc_S_rtc_40002800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_40002800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_40002800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/dma@40020000
 *
 * Node identifier: DT_N_S_soc_S_dma_40020000
 *
 * Binding (compatible = st,stm32-dma-v2):
 *   $ZEPHYR_BASE/dts/bindings/dma/st,stm32-dma-v2.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dma_40020000_PATH "/soc/dma@40020000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dma_40020000_FULL_NAME "dma@40020000"
#define DT_N_S_soc_S_dma_40020000_FULL_NAME_UNQUOTED dma@40020000
#define DT_N_S_soc_S_dma_40020000_FULL_NAME_TOKEN dma_40020000
#define DT_N_S_soc_S_dma_40020000_FULL_NAME_UPPER_TOKEN DMA_40020000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dma_40020000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dma_40020000_CHILD_IDX 38

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dma_40020000_NODELABEL_NUM 1
#define DT_N_S_soc_S_dma_40020000_FOREACH_NODELABEL(fn) fn(dma1)
#define DT_N_S_soc_S_dma_40020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma1, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dma_40020000_CHILD_NUM 0
#define DT_N_S_soc_S_dma_40020000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dma_40020000_HASH wrD_czGB0R3hBC1Od9iGdfNbQ3BZqmarPsJAc4MBFAs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dma_40020000_ORD 68
#define DT_N_S_soc_S_dma_40020000_ORD_STR_SORTABLE 00068

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dma_40020000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dma_40020000_SUPPORTS_ORDS \
	69, /* /soc/sai1@40015404 */ \
	70, /* /soc/sai1@40015424 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dma_40020000_EXISTS 1
#define DT_N_INST_0_st_stm32_dma_v2 DT_N_S_soc_S_dma_40020000
#define DT_N_NODELABEL_dma1         DT_N_S_soc_S_dma_40020000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dma_40020000_REG_NUM 1
#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */
#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_dma_40020000_FOREACH_REG(fn) fn(DT_N_S_soc_S_dma_40020000, 0)
#define DT_N_S_soc_S_dma_40020000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, 0)
#define DT_N_S_soc_S_dma_40020000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_RANGES_NUM 0
#define DT_N_S_soc_S_dma_40020000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dma_40020000_IRQ_NUM 6
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_irq 12
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_irq 13
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_irq 14
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_irq 15
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_irq 16
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_dma_40020000_IRQ_LEVEL 1
#define DT_N_S_soc_S_dma_40020000_COMPAT_MATCHES_st_stm32_dma_v2 1
#define DT_N_S_soc_S_dma_40020000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_dma_40020000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_COMPAT_MODEL_IDX_0 "stm32-dma-v2"
#define DT_N_S_soc_S_dma_40020000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dma_40020000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dma_40020000_P_reg {1073872896 /* 0x40020000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0 1073872896
#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_dma_40020000_P_reg_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts {11 /* 0xb */, 0 /* 0x0 */, 12 /* 0xc */, 0 /* 0x0 */, 13 /* 0xd */, 0 /* 0x0 */, 14 /* 0xe */, 0 /* 0x0 */, 15 /* 0xf */, 0 /* 0x0 */, 16 /* 0x10 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2 12
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4 13
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6 14
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8 15
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9 0
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10 16
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11 0
#define DT_N_S_soc_S_dma_40020000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem 0
#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_dma_offset 0
#define DT_N_S_soc_S_dma_40020000_P_dma_offset_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_dma_requests 6
#define DT_N_S_soc_S_dma_40020000_P_dma_requests_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_status "disabled"
#define DT_N_S_soc_S_dma_40020000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_dma_40020000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_dma_40020000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, status, 0)
#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, status, 0)
#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_P_status_LEN 1
#define DT_N_S_soc_S_dma_40020000_P_status_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_compatible {"st,stm32-dma-v2"}
#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0 "st,stm32-dma-v2"
#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v2
#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v2
#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V2
#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, compatible, 0)
#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, compatible, 0)
#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_P_compatible_LEN 1
#define DT_N_S_soc_S_dma_40020000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus 72
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_dma_40020000, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_dma_40020000, clocks, 0, bits)
#define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, clocks, 0)
#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, clocks, 0)
#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_40020000_P_clocks_LEN 1
#define DT_N_S_soc_S_dma_40020000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_dma_coherent 0
#define DT_N_S_soc_S_dma_40020000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_wakeup_source 0
#define DT_N_S_soc_S_dma_40020000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sai1@40015404
 *
 * Node identifier: DT_N_S_soc_S_sai1_40015404
 *
 * Binding (compatible = st,stm32-sai):
 *   $ZEPHYR_BASE/dts/bindings/i2s/st,stm32-sai.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sai1_40015404_PATH "/soc/sai1@40015404"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sai1_40015404_FULL_NAME "sai1@40015404"
#define DT_N_S_soc_S_sai1_40015404_FULL_NAME_UNQUOTED sai1@40015404
#define DT_N_S_soc_S_sai1_40015404_FULL_NAME_TOKEN sai1_40015404
#define DT_N_S_soc_S_sai1_40015404_FULL_NAME_UPPER_TOKEN SAI1_40015404

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_sai1_40015404_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sai1_40015404_CHILD_IDX 42

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sai1_40015404_NODELABEL_NUM 1
#define DT_N_S_soc_S_sai1_40015404_FOREACH_NODELABEL(fn) fn(sai1_a)
#define DT_N_S_soc_S_sai1_40015404_FOREACH_NODELABEL_VARGS(fn, ...) fn(sai1_a, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sai1_40015404_CHILD_NUM 0
#define DT_N_S_soc_S_sai1_40015404_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015404_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sai1_40015404_HASH Qeylb4uqfwx89IEioEsHJ7zY_NzeUuHabDztzaQ1AC4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sai1_40015404_ORD 69
#define DT_N_S_soc_S_sai1_40015404_ORD_STR_SORTABLE 00069

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sai1_40015404_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */ \
	68, /* /soc/dma@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sai1_40015404_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sai1_40015404_EXISTS 1
#define DT_N_INST_0_st_stm32_sai DT_N_S_soc_S_sai1_40015404
#define DT_N_NODELABEL_sai1_a    DT_N_S_soc_S_sai1_40015404

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sai1_40015404_REG_NUM 1
#define DT_N_S_soc_S_sai1_40015404_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_REG_IDX_0_VAL_ADDRESS 1073828868 /* 0x40015404 */
#define DT_N_S_soc_S_sai1_40015404_REG_IDX_0_VAL_SIZE 32 /* 0x20 */
#define DT_N_S_soc_S_sai1_40015404_FOREACH_REG(fn) fn(DT_N_S_soc_S_sai1_40015404, 0)
#define DT_N_S_soc_S_sai1_40015404_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, 0)
#define DT_N_S_soc_S_sai1_40015404_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_RANGES_NUM 0
#define DT_N_S_soc_S_sai1_40015404_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sai1_40015404_IRQ_NUM 0
#define DT_N_S_soc_S_sai1_40015404_IRQ_LEVEL 0
#define DT_N_S_soc_S_sai1_40015404_COMPAT_MATCHES_st_stm32_sai 1
#define DT_N_S_soc_S_sai1_40015404_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_sai1_40015404_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_COMPAT_MODEL_IDX_0 "stm32-sai"
#define DT_N_S_soc_S_sai1_40015404_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sai1_40015404_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sai1_40015404_P_reg {1073828868 /* 0x40015404 */, 32 /* 0x20 */}
#define DT_N_S_soc_S_sai1_40015404_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_reg_IDX_0 1073828868
#define DT_N_S_soc_S_sai1_40015404_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_reg_IDX_1 32
#define DT_N_S_soc_S_sai1_40015404_P_reg_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40020000
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_VAL_channel 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_VAL_slot 108
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_VAL_channel_config 141312
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, channel) \
	fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, slot) \
	fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, channel-config)
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, channel-config)
#define DT_N_S_soc_S_sai1_40015404_P_dmas_IDX_0_NUM_CELLS 3
#define DT_N_S_soc_S_sai1_40015404_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015404, dmas, 0)
#define DT_N_S_soc_S_sai1_40015404_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, dmas, 0)
#define DT_N_S_soc_S_sai1_40015404_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_dmas_LEN 1
#define DT_N_S_soc_S_sai1_40015404_P_dmas_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_mclk_enable 0
#define DT_N_S_soc_S_sai1_40015404_P_mclk_enable_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider "no-div"
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_STRING_UNQUOTED no-div
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_STRING_TOKEN no_div
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_STRING_UPPER_TOKEN NO_DIV
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_IDX_0 "no-div"
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_IDX_0_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015404, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_LEN 1
#define DT_N_S_soc_S_sai1_40015404_P_mclk_divider_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_synchronous 0
#define DT_N_S_soc_S_sai1_40015404_P_synchronous_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold "full"
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_STRING_UNQUOTED full
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_STRING_TOKEN full
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_STRING_UPPER_TOKEN FULL
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_IDX_0 "full"
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_IDX_0_ENUM_IDX 4
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_IDX_0_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015404, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_LEN 1
#define DT_N_S_soc_S_sai1_40015404_P_fifo_threshold_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_status "disabled"
#define DT_N_S_soc_S_sai1_40015404_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sai1_40015404_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sai1_40015404_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sai1_40015404_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sai1_40015404_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sai1_40015404_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015404, status, 0)
#define DT_N_S_soc_S_sai1_40015404_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, status, 0)
#define DT_N_S_soc_S_sai1_40015404_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_status_LEN 1
#define DT_N_S_soc_S_sai1_40015404_P_status_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_compatible {"st,stm32-sai"}
#define DT_N_S_soc_S_sai1_40015404_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_compatible_IDX_0 "st,stm32-sai"
#define DT_N_S_soc_S_sai1_40015404_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sai
#define DT_N_S_soc_S_sai1_40015404_P_compatible_IDX_0_STRING_TOKEN st_stm32_sai
#define DT_N_S_soc_S_sai1_40015404_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SAI
#define DT_N_S_soc_S_sai1_40015404_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015404, compatible, 0)
#define DT_N_S_soc_S_sai1_40015404_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, compatible, 0)
#define DT_N_S_soc_S_sai1_40015404_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_compatible_LEN 1
#define DT_N_S_soc_S_sai1_40015404_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_VAL_bits 2097152
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015404, clocks, 0, bus) \
	fn(DT_N_S_soc_S_sai1_40015404, clocks, 0, bits)
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015404, clocks, 0, bits)
#define DT_N_S_soc_S_sai1_40015404_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_sai1_40015404_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015404, clocks, 0)
#define DT_N_S_soc_S_sai1_40015404_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015404, clocks, 0)
#define DT_N_S_soc_S_sai1_40015404_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015404, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015404, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015404_P_clocks_LEN 1
#define DT_N_S_soc_S_sai1_40015404_P_clocks_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_dma_coherent 0
#define DT_N_S_soc_S_sai1_40015404_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sai1_40015404_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_wakeup_source 0
#define DT_N_S_soc_S_sai1_40015404_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sai1_40015404_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sai1_40015404_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sai1@40015424
 *
 * Node identifier: DT_N_S_soc_S_sai1_40015424
 *
 * Binding (compatible = st,stm32-sai):
 *   $ZEPHYR_BASE/dts/bindings/i2s/st,stm32-sai.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sai1_40015424_PATH "/soc/sai1@40015424"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sai1_40015424_FULL_NAME "sai1@40015424"
#define DT_N_S_soc_S_sai1_40015424_FULL_NAME_UNQUOTED sai1@40015424
#define DT_N_S_soc_S_sai1_40015424_FULL_NAME_TOKEN sai1_40015424
#define DT_N_S_soc_S_sai1_40015424_FULL_NAME_UPPER_TOKEN SAI1_40015424

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_sai1_40015424_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sai1_40015424_CHILD_IDX 43

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sai1_40015424_NODELABEL_NUM 1
#define DT_N_S_soc_S_sai1_40015424_FOREACH_NODELABEL(fn) fn(sai1_b)
#define DT_N_S_soc_S_sai1_40015424_FOREACH_NODELABEL_VARGS(fn, ...) fn(sai1_b, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sai1_40015424_CHILD_NUM 0
#define DT_N_S_soc_S_sai1_40015424_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sai1_40015424_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sai1_40015424_HASH SB_xxcHcj4kwx_SBJjUxUtYBpvfeKkpofD2o9QYZc5E

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sai1_40015424_ORD 70
#define DT_N_S_soc_S_sai1_40015424_ORD_STR_SORTABLE 00070

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sai1_40015424_REQUIRES_ORDS \
	4, /* /soc */ \
	9, /* /soc/rcc@40021000 */ \
	68, /* /soc/dma@40020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sai1_40015424_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sai1_40015424_EXISTS 1
#define DT_N_INST_1_st_stm32_sai DT_N_S_soc_S_sai1_40015424
#define DT_N_NODELABEL_sai1_b    DT_N_S_soc_S_sai1_40015424

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sai1_40015424_REG_NUM 1
#define DT_N_S_soc_S_sai1_40015424_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_REG_IDX_0_VAL_ADDRESS 1073828900 /* 0x40015424 */
#define DT_N_S_soc_S_sai1_40015424_REG_IDX_0_VAL_SIZE 32 /* 0x20 */
#define DT_N_S_soc_S_sai1_40015424_FOREACH_REG(fn) fn(DT_N_S_soc_S_sai1_40015424, 0)
#define DT_N_S_soc_S_sai1_40015424_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, 0)
#define DT_N_S_soc_S_sai1_40015424_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_RANGES_NUM 0
#define DT_N_S_soc_S_sai1_40015424_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sai1_40015424_IRQ_NUM 0
#define DT_N_S_soc_S_sai1_40015424_IRQ_LEVEL 0
#define DT_N_S_soc_S_sai1_40015424_COMPAT_MATCHES_st_stm32_sai 1
#define DT_N_S_soc_S_sai1_40015424_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_sai1_40015424_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_COMPAT_MODEL_IDX_0 "stm32-sai"
#define DT_N_S_soc_S_sai1_40015424_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sai1_40015424_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sai1_40015424_P_reg {1073828900 /* 0x40015424 */, 32 /* 0x20 */}
#define DT_N_S_soc_S_sai1_40015424_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_reg_IDX_0 1073828900
#define DT_N_S_soc_S_sai1_40015424_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_reg_IDX_1 32
#define DT_N_S_soc_S_sai1_40015424_P_reg_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40020000
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_VAL_channel 2
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_VAL_slot 109
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_VAL_slot_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_VAL_channel_config 141312
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_VAL_channel_config_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, channel) \
	fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, slot) \
	fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, channel-config)
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, channel) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, slot) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, channel-config)
#define DT_N_S_soc_S_sai1_40015424_P_dmas_IDX_0_NUM_CELLS 3
#define DT_N_S_soc_S_sai1_40015424_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015424, dmas, 0)
#define DT_N_S_soc_S_sai1_40015424_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, dmas, 0)
#define DT_N_S_soc_S_sai1_40015424_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, dmas, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_dmas_LEN 1
#define DT_N_S_soc_S_sai1_40015424_P_dmas_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_mclk_enable 0
#define DT_N_S_soc_S_sai1_40015424_P_mclk_enable_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider "no-div"
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_STRING_UNQUOTED no-div
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_STRING_TOKEN no_div
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_STRING_UPPER_TOKEN NO_DIV
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_IDX_0 "no-div"
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_IDX_0_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_ENUM_VAL_no_div_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015424, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, mclk_divider, 0)
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, mclk_divider, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_LEN 1
#define DT_N_S_soc_S_sai1_40015424_P_mclk_divider_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_synchronous 0
#define DT_N_S_soc_S_sai1_40015424_P_synchronous_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold "full"
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_STRING_UNQUOTED full
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_STRING_TOKEN full
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_STRING_UPPER_TOKEN FULL
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_IDX_0 "full"
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_IDX_0_ENUM_IDX 4
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_IDX_0_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_ENUM_VAL_full_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015424, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, fifo_threshold, 0)
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, fifo_threshold, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_LEN 1
#define DT_N_S_soc_S_sai1_40015424_P_fifo_threshold_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_status "disabled"
#define DT_N_S_soc_S_sai1_40015424_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sai1_40015424_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sai1_40015424_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sai1_40015424_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sai1_40015424_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sai1_40015424_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015424, status, 0)
#define DT_N_S_soc_S_sai1_40015424_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, status, 0)
#define DT_N_S_soc_S_sai1_40015424_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_status_LEN 1
#define DT_N_S_soc_S_sai1_40015424_P_status_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_compatible {"st,stm32-sai"}
#define DT_N_S_soc_S_sai1_40015424_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_compatible_IDX_0 "st,stm32-sai"
#define DT_N_S_soc_S_sai1_40015424_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sai
#define DT_N_S_soc_S_sai1_40015424_P_compatible_IDX_0_STRING_TOKEN st_stm32_sai
#define DT_N_S_soc_S_sai1_40015424_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SAI
#define DT_N_S_soc_S_sai1_40015424_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015424, compatible, 0)
#define DT_N_S_soc_S_sai1_40015424_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, compatible, 0)
#define DT_N_S_soc_S_sai1_40015424_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_compatible_LEN 1
#define DT_N_S_soc_S_sai1_40015424_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_VAL_bits 2097152
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sai1_40015424, clocks, 0, bus) \
	fn(DT_N_S_soc_S_sai1_40015424, clocks, 0, bits)
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_sai1_40015424, clocks, 0, bits)
#define DT_N_S_soc_S_sai1_40015424_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_sai1_40015424_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sai1_40015424, clocks, 0)
#define DT_N_S_soc_S_sai1_40015424_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sai1_40015424, clocks, 0)
#define DT_N_S_soc_S_sai1_40015424_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sai1_40015424, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sai1_40015424, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sai1_40015424_P_clocks_LEN 1
#define DT_N_S_soc_S_sai1_40015424_P_clocks_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_dma_coherent 0
#define DT_N_S_soc_S_sai1_40015424_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sai1_40015424_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_wakeup_source 0
#define DT_N_S_soc_S_sai1_40015424_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sai1_40015424_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sai1_40015424_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/serial@40004400
 *
 * Node identifier: DT_N_S_soc_S_serial_40004400
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE/dts/bindings/serial/st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40004400_PATH "/soc/serial@40004400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40004400_FULL_NAME "serial@40004400"
#define DT_N_S_soc_S_serial_40004400_FULL_NAME_UNQUOTED serial@40004400
#define DT_N_S_soc_S_serial_40004400_FULL_NAME_TOKEN serial_40004400
#define DT_N_S_soc_S_serial_40004400_FULL_NAME_UPPER_TOKEN SERIAL_40004400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40004400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40004400_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40004400_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40004400_FOREACH_NODELABEL(fn) fn(usart2)
#define DT_N_S_soc_S_serial_40004400_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart2, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40004400_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40004400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40004400_HASH w0whRjCvTBPyVty9dxjB3Bsl1nzzH1xRQTJifgUAAKQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40004400_ORD 71
#define DT_N_S_soc_S_serial_40004400_ORD_STR_SORTABLE 00071

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40004400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40004400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40004400_EXISTS 1
#define DT_N_INST_1_st_stm32_usart DT_N_S_soc_S_serial_40004400
#define DT_N_INST_2_st_stm32_uart  DT_N_S_soc_S_serial_40004400
#define DT_N_NODELABEL_usart2      DT_N_S_soc_S_serial_40004400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40004400_REG_NUM 1
#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_ADDRESS 1073759232 /* 0x40004400 */
#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40004400, 0)
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, 0)
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40004400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40004400_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40004400_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40004400_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40004400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40004400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40004400_P_reg {1073759232 /* 0x40004400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0 1073759232
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40004400_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bits 131072
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004400, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, clocks, 0)
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, clocks, 0)
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id 1809
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004400, resets, 0, id)
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, resets, 0, id)
#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, resets, 0)
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, resets, 0)
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_interrupts {38 /* 0x26 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40004400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_current_speed 115200
#define DT_N_S_soc_S_serial_40004400_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits 8
#define DT_N_S_soc_S_serial_40004400_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40004400_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_single_wire 0
#define DT_N_S_soc_S_serial_40004400_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_enable 0
#define DT_N_S_soc_S_serial_40004400_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40004400_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40004400_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_de_invert 0
#define DT_N_S_soc_S_serial_40004400_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40004400_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity "none"
#define DT_N_S_soc_S_serial_40004400_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40004400_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40004400_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004400_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, parity, 0)
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, parity, 0)
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status "disabled"
#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40004400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, status, 0)
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, status, 0)
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_status_LEN 1
#define DT_N_S_soc_S_serial_40004400_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1)
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1)
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004400_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40004400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40004400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40004400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_tx_invert 0
#define DT_N_S_soc_S_serial_40004400_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004400_P_rx_invert 0
#define DT_N_S_soc_S_serial_40004400_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40004800
 *
 * Node identifier: DT_N_S_soc_S_serial_40004800
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE/dts/bindings/serial/st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40004800_PATH "/soc/serial@40004800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40004800_FULL_NAME "serial@40004800"
#define DT_N_S_soc_S_serial_40004800_FULL_NAME_UNQUOTED serial@40004800
#define DT_N_S_soc_S_serial_40004800_FULL_NAME_TOKEN serial_40004800
#define DT_N_S_soc_S_serial_40004800_FULL_NAME_UPPER_TOKEN SERIAL_40004800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40004800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40004800_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40004800_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40004800_FOREACH_NODELABEL(fn) fn(usart3)
#define DT_N_S_soc_S_serial_40004800_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart3, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40004800_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40004800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40004800_HASH zEiuovs75QHyumn1pL5rvTd5x6H1bdnak278L4bYuj0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40004800_ORD 72
#define DT_N_S_soc_S_serial_40004800_ORD_STR_SORTABLE 00072

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40004800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40004800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40004800_EXISTS 1
#define DT_N_INST_2_st_stm32_usart DT_N_S_soc_S_serial_40004800
#define DT_N_INST_3_st_stm32_uart  DT_N_S_soc_S_serial_40004800
#define DT_N_NODELABEL_usart3      DT_N_S_soc_S_serial_40004800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40004800_REG_NUM 1
#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_ADDRESS 1073760256 /* 0x40004800 */
#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40004800, 0)
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, 0)
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40004800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40004800_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_irq 39
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40004800_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40004800_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40004800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40004800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40004800_P_reg {1073760256 /* 0x40004800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0 1073760256
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40004800_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bits 262144
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, clocks, 0)
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, clocks, 0)
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_VAL_id 1810
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004800, resets, 0, id)
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, resets, 0, id)
#define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, resets, 0)
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, resets, 0)
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_interrupts {39 /* 0x27 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0 39
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40004800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_current_speed 115200
#define DT_N_S_soc_S_serial_40004800_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits 8
#define DT_N_S_soc_S_serial_40004800_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40004800_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_single_wire 0
#define DT_N_S_soc_S_serial_40004800_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40004800_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_enable 0
#define DT_N_S_soc_S_serial_40004800_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40004800_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40004800_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_de_invert 0
#define DT_N_S_soc_S_serial_40004800_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40004800_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity "none"
#define DT_N_S_soc_S_serial_40004800_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40004800_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40004800_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004800_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, parity, 0)
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, parity, 0)
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status "disabled"
#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40004800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, status, 0)
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, status, 0)
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_status_LEN 1
#define DT_N_S_soc_S_serial_40004800_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1)
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1)
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004800_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40004800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40004800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40004800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_tx_invert 0
#define DT_N_S_soc_S_serial_40004800_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004800_P_rx_invert 0
#define DT_N_S_soc_S_serial_40004800_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/serial@40004c00
 *
 * Node identifier: DT_N_S_soc_S_serial_40004c00
 *
 * Binding (compatible = st,stm32-uart):
 *   $ZEPHYR_BASE/dts/bindings/serial/st,stm32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40004c00_PATH "/soc/serial@40004c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME "serial@40004c00"
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_UNQUOTED serial@40004c00
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_TOKEN serial_40004c00
#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_UPPER_TOKEN SERIAL_40004C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40004c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40004c00_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40004c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40004c00_FOREACH_NODELABEL(fn) fn(uart4)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart4, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40004c00_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40004c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40004c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40004c00_HASH qw6sySCqGO4wCPwXm_EFlFNv1NqVYdGrZFXhKaRqK7U

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40004c00_ORD 73
#define DT_N_S_soc_S_serial_40004c00_ORD_STR_SORTABLE 00073

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40004c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40004c00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40004c00_EXISTS 1
#define DT_N_INST_4_st_stm32_uart DT_N_S_soc_S_serial_40004c00
#define DT_N_NODELABEL_uart4      DT_N_S_soc_S_serial_40004c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40004c00_REG_NUM 1
#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_ADDRESS 1073761280 /* 0x40004c00 */
#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40004c00, 0)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, 0)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40004c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40004c00_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_irq 52
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40004c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40004c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_COMPAT_MODEL_IDX_0 "stm32-uart"
#define DT_N_S_soc_S_serial_40004c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40004c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40004c00_P_reg {1073761280 /* 0x40004c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0 1073761280
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40004c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bits 524288
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id 1811
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, id)
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, id)
#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, resets, 0)
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, resets, 0)
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_interrupts {52 /* 0x34 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0 52
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40004c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_current_speed 115200
#define DT_N_S_soc_S_serial_40004c00_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits 8
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_single_wire 0
#define DT_N_S_soc_S_serial_40004c00_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_enable 0
#define DT_N_S_soc_S_serial_40004c00_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40004c00_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40004c00_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_de_invert 0
#define DT_N_S_soc_S_serial_40004c00_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40004c00_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity "none"
#define DT_N_S_soc_S_serial_40004c00_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40004c00_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40004c00_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40004c00_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, parity, 0)
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, parity, 0)
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status "disabled"
#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, status, 0)
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, status, 0)
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_status_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_compatible {"st,stm32-uart"}
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40004c00_P_compatible_LEN 1
#define DT_N_S_soc_S_serial_40004c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40004c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_tx_invert 0
#define DT_N_S_soc_S_serial_40004c00_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40004c00_P_rx_invert 0
#define DT_N_S_soc_S_serial_40004c00_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/lpuart1_rx_pa3
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_PATH "/soc/pin-controller@48000000/lpuart1_rx_pa3"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FULL_NAME "lpuart1_rx_pa3"
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FULL_NAME_UNQUOTED lpuart1_rx_pa3
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FULL_NAME_TOKEN lpuart1_rx_pa3
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FULL_NAME_UPPER_TOKEN LPUART1_RX_PA3

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_NODELABEL(fn) fn(lpuart1_rx_pa3)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_NODELABEL_VARGS(fn, ...) fn(lpuart1_rx_pa3, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_HASH WyQwh28Pr7J_cdzFkBQs8QI_d1PxE3Pm7VJGqLte_Tk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_ORD 74
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_ORD_STR_SORTABLE 00074

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_SUPPORTS_ORDS \
	76, /* /soc/serial@40008000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_EXISTS 1
#define DT_N_NODELABEL_lpuart1_rx_pa3 DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_pinmux 108
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/lpuart1_tx_pa2
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_PATH "/soc/pin-controller@48000000/lpuart1_tx_pa2"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FULL_NAME "lpuart1_tx_pa2"
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FULL_NAME_UNQUOTED lpuart1_tx_pa2
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FULL_NAME_TOKEN lpuart1_tx_pa2
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FULL_NAME_UPPER_TOKEN LPUART1_TX_PA2

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_NODELABEL(fn) fn(lpuart1_tx_pa2)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_NODELABEL_VARGS(fn, ...) fn(lpuart1_tx_pa2, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_HASH xN8qvyYfTBX7qNR9778uABa0MaMxHEEShKRfepH4hSs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_ORD 75
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_ORD_STR_SORTABLE 00075

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_SUPPORTS_ORDS \
	76, /* /soc/serial@40008000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_EXISTS 1
#define DT_N_NODELABEL_lpuart1_tx_pa2 DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_pinmux 76
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/serial@40008000
 *
 * Node identifier: DT_N_S_soc_S_serial_40008000
 *
 * Binding (compatible = st,stm32-lpuart):
 *   $ZEPHYR_BASE/dts/bindings/serial/st,stm32-lpuart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40008000_PATH "/soc/serial@40008000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40008000_FULL_NAME "serial@40008000"
#define DT_N_S_soc_S_serial_40008000_FULL_NAME_UNQUOTED serial@40008000
#define DT_N_S_soc_S_serial_40008000_FULL_NAME_TOKEN serial_40008000
#define DT_N_S_soc_S_serial_40008000_FULL_NAME_UPPER_TOKEN SERIAL_40008000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40008000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40008000_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40008000_NODELABEL_NUM 1
#define DT_N_S_soc_S_serial_40008000_FOREACH_NODELABEL(fn) fn(lpuart1)
#define DT_N_S_soc_S_serial_40008000_FOREACH_NODELABEL_VARGS(fn, ...) fn(lpuart1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40008000_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40008000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40008000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40008000_HASH m3LA5ahuvua6JbY3wkM444Ci5dNOInJTrqWFcetRNbo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40008000_ORD 76
#define DT_N_S_soc_S_serial_40008000_ORD_STR_SORTABLE 00076

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40008000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */ \
	74, /* /soc/pin-controller@48000000/lpuart1_rx_pa3 */ \
	75, /* /soc/pin-controller@48000000/lpuart1_tx_pa2 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40008000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40008000_EXISTS 1
#define DT_N_INST_0_st_stm32_lpuart DT_N_S_soc_S_serial_40008000
#define DT_N_INST_1_st_stm32_uart   DT_N_S_soc_S_serial_40008000
#define DT_N_NODELABEL_lpuart1      DT_N_S_soc_S_serial_40008000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40008000_REG_NUM 1
#define DT_N_S_soc_S_serial_40008000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_REG_IDX_0_VAL_ADDRESS 1073774592 /* 0x40008000 */
#define DT_N_S_soc_S_serial_40008000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40008000_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40008000, 0)
#define DT_N_S_soc_S_serial_40008000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, 0)
#define DT_N_S_soc_S_serial_40008000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40008000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40008000_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_VAL_irq 91
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40008000_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_MATCHES_st_stm32_lpuart 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40008000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_MODEL_IDX_0 "stm32-lpuart"
#define DT_N_S_soc_S_serial_40008000_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40008000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40008000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40008000_PINCTRL_NUM 1
#define DT_N_S_soc_S_serial_40008000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_serial_40008000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40008000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_serial_40008000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2
#define DT_N_S_soc_S_serial_40008000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40008000_P_reg {1073774592 /* 0x40008000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40008000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_reg_IDX_0 1073774592
#define DT_N_S_soc_S_serial_40008000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40008000_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_VAL_bus 92
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_VAL_bits 1
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40008000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40008000, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40008000, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40008000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40008000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, clocks, 0)
#define DT_N_S_soc_S_serial_40008000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, clocks, 0)
#define DT_N_S_soc_S_serial_40008000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40008000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_VAL_id 1920
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40008000, resets, 0, id)
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, resets, 0, id)
#define DT_N_S_soc_S_serial_40008000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40008000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, resets, 0)
#define DT_N_S_soc_S_serial_40008000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, resets, 0)
#define DT_N_S_soc_S_serial_40008000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40008000_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_interrupts {91 /* 0x5b */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40008000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_interrupts_IDX_0 91
#define DT_N_S_soc_S_serial_40008000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40008000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_current_speed 115200
#define DT_N_S_soc_S_serial_40008000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, stop_bits, 0)
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, stop_bits, 0)
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40008000_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_data_bits 8
#define DT_N_S_soc_S_serial_40008000_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40008000_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_single_wire 0
#define DT_N_S_soc_S_serial_40008000_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40008000_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40008000, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_serial_40008000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_de_enable 0
#define DT_N_S_soc_S_serial_40008000_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40008000_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40008000_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_de_invert 0
#define DT_N_S_soc_S_serial_40008000_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40008000_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40008000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_parity "none"
#define DT_N_S_soc_S_serial_40008000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40008000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40008000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40008000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40008000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40008000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, parity, 0)
#define DT_N_S_soc_S_serial_40008000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, parity, 0)
#define DT_N_S_soc_S_serial_40008000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40008000_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_status "okay"
#define DT_N_S_soc_S_serial_40008000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_serial_40008000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_serial_40008000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_serial_40008000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_serial_40008000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40008000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, status, 0)
#define DT_N_S_soc_S_serial_40008000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, status, 0)
#define DT_N_S_soc_S_serial_40008000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_status_LEN 1
#define DT_N_S_soc_S_serial_40008000_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_compatible {"st,stm32-lpuart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_0 "st,stm32-lpuart"
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lpuart
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_0_STRING_TOKEN st_stm32_lpuart
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LPUART
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40008000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40008000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40008000, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40008000, compatible, 1)
#define DT_N_S_soc_S_serial_40008000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40008000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40008000, compatible, 1)
#define DT_N_S_soc_S_serial_40008000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40008000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40008000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40008000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40008000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40008000_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40008000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40008000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40008000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40008000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40008000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_tx_invert 0
#define DT_N_S_soc_S_serial_40008000_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40008000_P_rx_invert 0
#define DT_N_S_soc_S_serial_40008000_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/usart1_rx_pc5
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_PATH "/soc/pin-controller@48000000/usart1_rx_pc5"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FULL_NAME "usart1_rx_pc5"
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FULL_NAME_UNQUOTED usart1_rx_pc5
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FULL_NAME_TOKEN usart1_rx_pc5
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FULL_NAME_UPPER_TOKEN USART1_RX_PC5

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_NODELABEL(fn) fn(usart1_rx_pc5)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart1_rx_pc5, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_HASH 0dk2RVBCCQexD9H__QpjdsAYkDmF_7b5onxntaqN7pQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_ORD 77
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_ORD_STR_SORTABLE 00077

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_SUPPORTS_ORDS \
	79, /* /soc/serial@40013800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_EXISTS 1
#define DT_N_NODELABEL_usart1_rx_pc5 DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_pinmux 1191
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/usart1_tx_pc4
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_PATH "/soc/pin-controller@48000000/usart1_tx_pc4"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FULL_NAME "usart1_tx_pc4"
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FULL_NAME_UNQUOTED usart1_tx_pc4
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FULL_NAME_TOKEN usart1_tx_pc4
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FULL_NAME_UPPER_TOKEN USART1_TX_PC4

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_NODELABEL(fn) fn(usart1_tx_pc4)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart1_tx_pc4, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_HASH tD4KrmMipAUPPosulSZ7bQ0d5GgJMXQCSkGG_ws_Drg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_ORD 78
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_ORD_STR_SORTABLE 00078

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_SUPPORTS_ORDS \
	79, /* /soc/serial@40013800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_EXISTS 1
#define DT_N_NODELABEL_usart1_tx_pc4 DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_pinmux 1159
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_STRING_UNQUOTED low-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_STRING_TOKEN low_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_IDX_0 "low-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/serial@40013800
 *
 * Node identifier: DT_N_S_soc_S_serial_40013800
 *
 * Binding (compatible = st,stm32-usart):
 *   $ZEPHYR_BASE/dts/bindings/serial/st,stm32-usart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_serial_40013800_PATH "/soc/serial@40013800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_serial_40013800_FULL_NAME "serial@40013800"
#define DT_N_S_soc_S_serial_40013800_FULL_NAME_UNQUOTED serial@40013800
#define DT_N_S_soc_S_serial_40013800_FULL_NAME_TOKEN serial_40013800
#define DT_N_S_soc_S_serial_40013800_FULL_NAME_UPPER_TOKEN SERIAL_40013800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_serial_40013800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_serial_40013800_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_serial_40013800_NODELABEL_NUM 2
#define DT_N_S_soc_S_serial_40013800_FOREACH_NODELABEL(fn) fn(usart1) fn(arduino_serial)
#define DT_N_S_soc_S_serial_40013800_FOREACH_NODELABEL_VARGS(fn, ...) fn(usart1, __VA_ARGS__) fn(arduino_serial, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_serial_40013800_CHILD_NUM 0
#define DT_N_S_soc_S_serial_40013800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_serial_40013800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_serial_40013800_HASH Ekd_nQjwNx1R3lqiZl1FuXwHyvPZFcfnjksadzf44zc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_serial_40013800_ORD 79
#define DT_N_S_soc_S_serial_40013800_ORD_STR_SORTABLE 00079

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_serial_40013800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */ \
	77, /* /soc/pin-controller@48000000/usart1_rx_pc5 */ \
	78, /* /soc/pin-controller@48000000/usart1_tx_pc4 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_serial_40013800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_serial_40013800_EXISTS 1
#define DT_N_INST_0_st_stm32_usart    DT_N_S_soc_S_serial_40013800
#define DT_N_INST_0_st_stm32_uart     DT_N_S_soc_S_serial_40013800
#define DT_N_NODELABEL_usart1         DT_N_S_soc_S_serial_40013800
#define DT_N_NODELABEL_arduino_serial DT_N_S_soc_S_serial_40013800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_serial_40013800_REG_NUM 1
#define DT_N_S_soc_S_serial_40013800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_REG_IDX_0_VAL_ADDRESS 1073821696 /* 0x40013800 */
#define DT_N_S_soc_S_serial_40013800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_serial_40013800_FOREACH_REG(fn) fn(DT_N_S_soc_S_serial_40013800, 0)
#define DT_N_S_soc_S_serial_40013800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, 0)
#define DT_N_S_soc_S_serial_40013800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_RANGES_NUM 0
#define DT_N_S_soc_S_serial_40013800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_serial_40013800_IRQ_NUM 1
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_VAL_irq 37
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_serial_40013800_IRQ_LEVEL 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_MATCHES_st_stm32_usart 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40013800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_MODEL_IDX_0 "stm32-usart"
#define DT_N_S_soc_S_serial_40013800_COMPAT_MATCHES_st_stm32_uart 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_serial_40013800_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_COMPAT_MODEL_IDX_1 "stm32-uart"
#define DT_N_S_soc_S_serial_40013800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_serial_40013800_PINCTRL_NUM 1
#define DT_N_S_soc_S_serial_40013800_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_serial_40013800_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40013800_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_serial_40013800_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4
#define DT_N_S_soc_S_serial_40013800_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5

/* Generic property macros: */
#define DT_N_S_soc_S_serial_40013800_P_reg {1073821696 /* 0x40013800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_serial_40013800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_reg_IDX_0 1073821696
#define DT_N_S_soc_S_serial_40013800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_serial_40013800_P_reg_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_VAL_bits 16384
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40013800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_serial_40013800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40013800, clocks, 0, bits)
#define DT_N_S_soc_S_serial_40013800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_serial_40013800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, clocks, 0)
#define DT_N_S_soc_S_serial_40013800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, clocks, 0)
#define DT_N_S_soc_S_serial_40013800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_clocks_LEN 1
#define DT_N_S_soc_S_serial_40013800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_VAL_id 2062
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_serial_40013800, resets, 0, id)
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, resets, 0, id)
#define DT_N_S_soc_S_serial_40013800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_serial_40013800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, resets, 0)
#define DT_N_S_soc_S_serial_40013800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, resets, 0)
#define DT_N_S_soc_S_serial_40013800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_resets_LEN 1
#define DT_N_S_soc_S_serial_40013800_P_resets_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_interrupts {37 /* 0x25 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_serial_40013800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_interrupts_IDX_0 37
#define DT_N_S_soc_S_serial_40013800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_serial_40013800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_current_speed 115200
#define DT_N_S_soc_S_serial_40013800_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits "1"
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, stop_bits, 0)
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_LEN 1
#define DT_N_S_soc_S_serial_40013800_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_data_bits 8
#define DT_N_S_soc_S_serial_40013800_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_serial_40013800_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_single_wire 0
#define DT_N_S_soc_S_serial_40013800_P_single_wire_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_tx_rx_swap 0
#define DT_N_S_soc_S_serial_40013800_P_tx_rx_swap_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 1)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40013800, pinctrl_0, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_LEN 2
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, pinctrl_names, 0)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_serial_40013800_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_de_enable 0
#define DT_N_S_soc_S_serial_40013800_P_de_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_de_assert_time 0
#define DT_N_S_soc_S_serial_40013800_P_de_assert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_de_deassert_time 0
#define DT_N_S_soc_S_serial_40013800_P_de_deassert_time_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_de_invert 0
#define DT_N_S_soc_S_serial_40013800_P_de_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_fifo_enable 0
#define DT_N_S_soc_S_serial_40013800_P_fifo_enable_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_hw_flow_control 0
#define DT_N_S_soc_S_serial_40013800_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_parity "none"
#define DT_N_S_soc_S_serial_40013800_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_serial_40013800_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_serial_40013800_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_serial_40013800_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_serial_40013800_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40013800_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, parity, 0)
#define DT_N_S_soc_S_serial_40013800_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, parity, 0)
#define DT_N_S_soc_S_serial_40013800_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_parity_LEN 1
#define DT_N_S_soc_S_serial_40013800_P_parity_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_status "okay"
#define DT_N_S_soc_S_serial_40013800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_serial_40013800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_serial_40013800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_serial_40013800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_serial_40013800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_serial_40013800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, status, 0)
#define DT_N_S_soc_S_serial_40013800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, status, 0)
#define DT_N_S_soc_S_serial_40013800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_status_LEN 1
#define DT_N_S_soc_S_serial_40013800_P_status_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_compatible {"st,stm32-usart", "st,stm32-uart"}
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_0 "st,stm32-usart"
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_1 "st,stm32-uart"
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart
#define DT_N_S_soc_S_serial_40013800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART
#define DT_N_S_soc_S_serial_40013800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40013800, compatible, 0) \
	fn(DT_N_S_soc_S_serial_40013800, compatible, 1)
#define DT_N_S_soc_S_serial_40013800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40013800, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40013800, compatible, 1)
#define DT_N_S_soc_S_serial_40013800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40013800, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_serial_40013800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40013800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_serial_40013800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_serial_40013800_P_compatible_LEN 2
#define DT_N_S_soc_S_serial_40013800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_dma_coherent 0
#define DT_N_S_soc_S_serial_40013800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_serial_40013800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_wakeup_source 0
#define DT_N_S_soc_S_serial_40013800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_serial_40013800_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_tx_invert 0
#define DT_N_S_soc_S_serial_40013800_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_serial_40013800_P_rx_invert 0
#define DT_N_S_soc_S_serial_40013800_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi2_miso_pb14
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_PATH "/soc/pin-controller@48000000/spi2_miso_pb14"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FULL_NAME "spi2_miso_pb14"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FULL_NAME_UNQUOTED spi2_miso_pb14
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FULL_NAME_TOKEN spi2_miso_pb14
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FULL_NAME_UPPER_TOKEN SPI2_MISO_PB14

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_NODELABEL(fn) fn(spi2_miso_pb14)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2_miso_pb14, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_HASH ah9KZEq8pTbCt8KF_zQQvbrpYogRH_38Brc6hRZs3AY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_ORD 80
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_ORD_STR_SORTABLE 00080

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_SUPPORTS_ORDS \
	84, /* /soc/spi@40003800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_EXISTS 1
#define DT_N_NODELABEL_spi2_miso_pb14 DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_pinmux 965
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi2_mosi_pb15
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_PATH "/soc/pin-controller@48000000/spi2_mosi_pb15"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FULL_NAME "spi2_mosi_pb15"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FULL_NAME_UNQUOTED spi2_mosi_pb15
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FULL_NAME_TOKEN spi2_mosi_pb15
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FULL_NAME_UPPER_TOKEN SPI2_MOSI_PB15

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_NODELABEL(fn) fn(spi2_mosi_pb15)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2_mosi_pb15, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_HASH _uZC7LHAtAeyivvLcEW51gAozg38rwrJ4pZkKUu1Oc4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_ORD 81
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_ORD_STR_SORTABLE 00081

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_SUPPORTS_ORDS \
	84, /* /soc/spi@40003800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_EXISTS 1
#define DT_N_NODELABEL_spi2_mosi_pb15 DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_pinmux 997
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi2_nss_pb12
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_PATH "/soc/pin-controller@48000000/spi2_nss_pb12"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FULL_NAME "spi2_nss_pb12"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FULL_NAME_UNQUOTED spi2_nss_pb12
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FULL_NAME_TOKEN spi2_nss_pb12
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FULL_NAME_UPPER_TOKEN SPI2_NSS_PB12

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_NODELABEL(fn) fn(spi2_nss_pb12)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2_nss_pb12, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_HASH xsINVmqP9etKPFQf2W49DGysEh7j4EWHnpoQd2amtbQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_ORD 82
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_ORD_STR_SORTABLE 00082

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_SUPPORTS_ORDS \
	84, /* /soc/spi@40003800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_EXISTS 1
#define DT_N_NODELABEL_spi2_nss_pb12 DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_pinmux 901
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi2_sck_pb13
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_PATH "/soc/pin-controller@48000000/spi2_sck_pb13"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FULL_NAME "spi2_sck_pb13"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FULL_NAME_UNQUOTED spi2_sck_pb13
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FULL_NAME_TOKEN spi2_sck_pb13
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FULL_NAME_UPPER_TOKEN SPI2_SCK_PB13

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_NODELABEL(fn) fn(spi2_sck_pb13)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2_sck_pb13, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_HASH ckCtIJToOj4zsF_Iu00LEtdP8BWGtdTkqv1Khj_yGks

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_ORD 83
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_ORD_STR_SORTABLE 00083

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_SUPPORTS_ORDS \
	84, /* /soc/spi@40003800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_EXISTS 1
#define DT_N_NODELABEL_spi2_sck_pb13 DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_pinmux 933
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/spi@40003800
 *
 * Node identifier: DT_N_S_soc_S_spi_40003800
 *
 * Binding (compatible = st,stm32-spi-fifo):
 *   $ZEPHYR_BASE/dts/bindings/spi/st,stm32-spi-fifo.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40003800_PATH "/soc/spi@40003800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40003800_FULL_NAME "spi@40003800"
#define DT_N_S_soc_S_spi_40003800_FULL_NAME_UNQUOTED spi@40003800
#define DT_N_S_soc_S_spi_40003800_FULL_NAME_TOKEN spi_40003800
#define DT_N_S_soc_S_spi_40003800_FULL_NAME_UPPER_TOKEN SPI_40003800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40003800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40003800_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40003800_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40003800_FOREACH_NODELABEL(fn) fn(spi2)
#define DT_N_S_soc_S_spi_40003800_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40003800_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40003800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40003800_HASH XKwnj_54XNd9o8CRTIG33G9j_T58zD9aWx_JOqtlec4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40003800_ORD 84
#define DT_N_S_soc_S_spi_40003800_ORD_STR_SORTABLE 00084

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40003800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	80, /* /soc/pin-controller@48000000/spi2_miso_pb14 */ \
	81, /* /soc/pin-controller@48000000/spi2_mosi_pb15 */ \
	82, /* /soc/pin-controller@48000000/spi2_nss_pb12 */ \
	83, /* /soc/pin-controller@48000000/spi2_sck_pb13 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40003800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40003800_EXISTS 1
#define DT_N_INST_1_st_stm32_spi_fifo DT_N_S_soc_S_spi_40003800
#define DT_N_INST_1_st_stm32_spi      DT_N_S_soc_S_spi_40003800
#define DT_N_NODELABEL_spi2           DT_N_S_soc_S_spi_40003800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40003800_REG_NUM 1
#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 /* 0x40003800 */
#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40003800, 0)
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, 0)
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40003800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40003800_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40003800_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_MATCHES_st_stm32_spi_fifo 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40003800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_MODEL_IDX_0 "stm32-spi-fifo"
#define DT_N_S_soc_S_spi_40003800_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40003800_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_COMPAT_MODEL_IDX_1 "stm32-spi"
#define DT_N_S_soc_S_spi_40003800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NUM 1
#define DT_N_S_soc_S_spi_40003800_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40003800_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NAME_default_IDX_2_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14
#define DT_N_S_soc_S_spi_40003800_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40003800_P_reg {1073756160 /* 0x40003800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0 1073756160
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40003800_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_interrupts {36 /* 0x24 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40003800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_2_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_IDX_3_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 1) \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 2) \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 3)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 3)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, pinctrl_0, 3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_LEN 4
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_ioswp 0
#define DT_N_S_soc_S_spi_40003800_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width "full-4-to-16-bit"
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_STRING_UNQUOTED full-4-to-16-bit
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_STRING_TOKEN full_4_to_16_bit
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_STRING_UPPER_TOKEN FULL_4_TO_16_BIT
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0 "full-4-to-16-bit"
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_IDX_0_ENUM_VAL_full_4_to_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_ENUM_VAL_full_4_to_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40003800_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status "okay"
#define DT_N_S_soc_S_spi_40003800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_40003800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_40003800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, status, 0)
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, status, 0)
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_status_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_compatible {"st,stm32-spi-fifo", "st,stm32-spi"}
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0 "st,stm32-spi-fifo"
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi-fifo
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi_fifo
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, compatible, 0) \
	fn(DT_N_S_soc_S_spi_40003800, compatible, 1)
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, compatible, 1)
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_compatible_LEN 2
#define DT_N_S_soc_S_spi_40003800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bits 16384
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003800, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, clocks, 0)
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, clocks, 0)
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003800_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40003800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40003800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40003800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40003800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi3_miso_pc11
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_PATH "/soc/pin-controller@48000000/spi3_miso_pc11"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FULL_NAME "spi3_miso_pc11"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FULL_NAME_UNQUOTED spi3_miso_pc11
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FULL_NAME_TOKEN spi3_miso_pc11
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FULL_NAME_UPPER_TOKEN SPI3_MISO_PC11

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_NODELABEL(fn) fn(spi3_miso_pc11)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_miso_pc11, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_HASH FtbFJN6KajFC_Y2Ozvj6bIVerZAMafUQzXHL9vueoco

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_ORD 85
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_ORD_STR_SORTABLE 00085

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_SUPPORTS_ORDS \
	89, /* /soc/spi@40003c00 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_EXISTS 1
#define DT_N_NODELABEL_spi3_miso_pc11 DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_pinmux 1382
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi3_mosi_pc12
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_PATH "/soc/pin-controller@48000000/spi3_mosi_pc12"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FULL_NAME "spi3_mosi_pc12"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FULL_NAME_UNQUOTED spi3_mosi_pc12
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FULL_NAME_TOKEN spi3_mosi_pc12
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FULL_NAME_UPPER_TOKEN SPI3_MOSI_PC12

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_NODELABEL(fn) fn(spi3_mosi_pc12)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_mosi_pc12, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_HASH zpX8Ga2pHg00q_JMV_4Vnu_WMJmRtmaAxHpI2bxEW7c

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_ORD 86
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_ORD_STR_SORTABLE 00086

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_SUPPORTS_ORDS \
	89, /* /soc/spi@40003c00 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_EXISTS 1
#define DT_N_NODELABEL_spi3_mosi_pc12 DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_pinmux 1414
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi3_nss_pa15
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_PATH "/soc/pin-controller@48000000/spi3_nss_pa15"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FULL_NAME "spi3_nss_pa15"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FULL_NAME_UNQUOTED spi3_nss_pa15
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FULL_NAME_TOKEN spi3_nss_pa15
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FULL_NAME_UPPER_TOKEN SPI3_NSS_PA15

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_NODELABEL(fn) fn(spi3_nss_pa15)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_nss_pa15, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_HASH mgRgfptxOk1syYQtCCFDmpqSK6WxMogUEzF5GkuvVu4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_ORD 87
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_ORD_STR_SORTABLE 00087

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_SUPPORTS_ORDS \
	89, /* /soc/spi@40003c00 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_EXISTS 1
#define DT_N_NODELABEL_spi3_nss_pa15 DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_pinmux 486
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_bias_pull_up 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_bias_pull_down 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi3_sck_pc10
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_PATH "/soc/pin-controller@48000000/spi3_sck_pc10"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FULL_NAME "spi3_sck_pc10"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FULL_NAME_UNQUOTED spi3_sck_pc10
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FULL_NAME_TOKEN spi3_sck_pc10
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FULL_NAME_UPPER_TOKEN SPI3_SCK_PC10

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_NODELABEL(fn) fn(spi3_sck_pc10)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3_sck_pc10, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_HASH xxIYyIXBDO5DzjFECQzCM1SMqsk5_1LEGyeE1IyOEL0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_ORD 88
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_ORD_STR_SORTABLE 00088

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_SUPPORTS_ORDS \
	89, /* /soc/spi@40003c00 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_EXISTS 1
#define DT_N_NODELABEL_spi3_sck_pc10 DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_pinmux 1350
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/spi@40003c00
 *
 * Node identifier: DT_N_S_soc_S_spi_40003c00
 *
 * Binding (compatible = st,stm32-spi-fifo):
 *   $ZEPHYR_BASE/dts/bindings/spi/st,stm32-spi-fifo.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40003c00_PATH "/soc/spi@40003c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME "spi@40003c00"
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_UNQUOTED spi@40003c00
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_TOKEN spi_40003c00
#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_UPPER_TOKEN SPI_40003C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40003c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40003c00_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40003c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_40003c00_FOREACH_NODELABEL(fn) fn(spi3)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40003c00_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40003c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40003c00_HASH 2ZRlHGHWIr4tSgRVkDzDHSiC22m9C4PVNAuFo8LU_0A

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40003c00_ORD 89
#define DT_N_S_soc_S_spi_40003c00_ORD_STR_SORTABLE 00089

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40003c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	85, /* /soc/pin-controller@48000000/spi3_miso_pc11 */ \
	86, /* /soc/pin-controller@48000000/spi3_mosi_pc12 */ \
	87, /* /soc/pin-controller@48000000/spi3_nss_pa15 */ \
	88, /* /soc/pin-controller@48000000/spi3_sck_pc10 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40003c00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40003c00_EXISTS 1
#define DT_N_INST_2_st_stm32_spi_fifo DT_N_S_soc_S_spi_40003c00
#define DT_N_INST_2_st_stm32_spi      DT_N_S_soc_S_spi_40003c00
#define DT_N_NODELABEL_spi3           DT_N_S_soc_S_spi_40003c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40003c00_REG_NUM 1
#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 /* 0x40003c00 */
#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40003c00, 0)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, 0)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40003c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40003c00_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_irq 51
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40003c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MATCHES_st_stm32_spi_fifo 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MODEL_IDX_0 "stm32-spi-fifo"
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_COMPAT_MODEL_IDX_1 "stm32-spi"
#define DT_N_S_soc_S_spi_40003c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NUM 1
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NAME_default_IDX_2_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11
#define DT_N_S_soc_S_spi_40003c00_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40003c00_P_reg {1073757184 /* 0x40003c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0 1073757184
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40003c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_interrupts {51 /* 0x33 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0 51
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40003c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_2_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_IDX_3_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 1) \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 2) \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 3)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 3)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, pinctrl_0, 3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_LEN 4
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_ioswp 0
#define DT_N_S_soc_S_spi_40003c00_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width "full-4-to-16-bit"
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_STRING_UNQUOTED full-4-to-16-bit
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_STRING_TOKEN full_4_to_16_bit
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_STRING_UPPER_TOKEN FULL_4_TO_16_BIT
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0 "full-4-to-16-bit"
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_IDX_0_ENUM_VAL_full_4_to_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_ENUM_VAL_full_4_to_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40003c00_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status "okay"
#define DT_N_S_soc_S_spi_40003c00_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_40003c00_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_40003c00_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, status, 0)
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, status, 0)
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_status_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_compatible {"st,stm32-spi-fifo", "st,stm32-spi"}
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0 "st,stm32-spi-fifo"
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi-fifo
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi_fifo
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0) \
	fn(DT_N_S_soc_S_spi_40003c00, compatible, 1)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, compatible, 1)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003c00, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_compatible_LEN 2
#define DT_N_S_soc_S_spi_40003c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bits 32768
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003c00_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40003c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40003c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48000400
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_PATH "/soc/pin-controller@48000000/gpio@48000400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FULL_NAME "gpio@48000400"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FULL_NAME_UNQUOTED gpio@48000400
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FULL_NAME_TOKEN gpio_48000400
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FULL_NAME_UPPER_TOKEN GPIO_48000400

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_NODELABEL(fn) fn(gpiob)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiob, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_HASH _ITOixrnsdulY77mYPcfDq4R1DIXVligCgZL7jMBzZg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_ORD 90
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_ORD_STR_SORTABLE 00090

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_SUPPORTS_ORDS \
	94, /* /soc/spi@40013000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_EXISTS 1
#define DT_N_INST_1_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_NODELABEL_gpiob      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_REG_IDX_0_VAL_ADDRESS 1207960576 /* 0x48000400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_reg {1207960576 /* 0x48000400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_reg_IDX_0 1207960576
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_VAL_bits 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi1_miso_pa6
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_PATH "/soc/pin-controller@48000000/spi1_miso_pa6"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FULL_NAME "spi1_miso_pa6"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FULL_NAME_UNQUOTED spi1_miso_pa6
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FULL_NAME_TOKEN spi1_miso_pa6
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FULL_NAME_UPPER_TOKEN SPI1_MISO_PA6

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_NODELABEL(fn) fn(spi1_miso_pa6)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_miso_pa6, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_HASH oIzkx4rl5Nz8vPvVzWtwu4yICDyfxXigFKVAM4TV97Y

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_ORD 91
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_ORD_STR_SORTABLE 00091

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_SUPPORTS_ORDS \
	94, /* /soc/spi@40013000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_EXISTS 1
#define DT_N_NODELABEL_spi1_miso_pa6 DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_pinmux 197
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi1_mosi_pa7
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_PATH "/soc/pin-controller@48000000/spi1_mosi_pa7"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FULL_NAME "spi1_mosi_pa7"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FULL_NAME_UNQUOTED spi1_mosi_pa7
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FULL_NAME_TOKEN spi1_mosi_pa7
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FULL_NAME_UPPER_TOKEN SPI1_MOSI_PA7

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_NODELABEL(fn) fn(spi1_mosi_pa7)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_mosi_pa7, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_HASH D3H8IMt40ZTRaaH4HvFRvGhMIv98zWAp5VYqnK_Yfb0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_ORD 92
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_ORD_STR_SORTABLE 00092

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_SUPPORTS_ORDS \
	94, /* /soc/spi@40013000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_EXISTS 1
#define DT_N_NODELABEL_spi1_mosi_pa7 DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_pinmux 229
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/spi1_sck_pa5
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_PATH "/soc/pin-controller@48000000/spi1_sck_pa5"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FULL_NAME "spi1_sck_pa5"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FULL_NAME_UNQUOTED spi1_sck_pa5
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FULL_NAME_TOKEN spi1_sck_pa5
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FULL_NAME_UPPER_TOKEN SPI1_SCK_PA5

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_NODELABEL(fn) fn(spi1_sck_pa5)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1_sck_pa5, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_HASH wPnATtGdEMkO_93Qu180QF012JwegU_R5_0R97wwnqc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_ORD 93
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_ORD_STR_SORTABLE 00093

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_REQUIRES_ORDS \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_SUPPORTS_ORDS \
	94, /* /soc/spi@40013000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_EXISTS 1
#define DT_N_NODELABEL_spi1_sck_pa5 DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_REG_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_REG(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_pinmux 165
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_pinmux_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_STRING_UNQUOTED very-high-speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_STRING_TOKEN very_high_speed
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_IDX_0 "very-high-speed"
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, slew_rate, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, slew_rate, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_slew_rate_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_bias_disable 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_bias_disable_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_bias_pull_up 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_bias_pull_up_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_bias_pull_down 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_bias_pull_down_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_drive_push_pull 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_drive_push_pull_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_drive_open_drain 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_drive_open_drain_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_output_low 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_output_low_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_output_high 0
#define DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5_P_output_high_EXISTS 1

/*
 * Devicetree node: /soc/spi@40013000
 *
 * Node identifier: DT_N_S_soc_S_spi_40013000
 *
 * Binding (compatible = st,stm32-spi-fifo):
 *   $ZEPHYR_BASE/dts/bindings/spi/st,stm32-spi-fifo.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40013000_PATH "/soc/spi@40013000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40013000_FULL_NAME "spi@40013000"
#define DT_N_S_soc_S_spi_40013000_FULL_NAME_UNQUOTED spi@40013000
#define DT_N_S_soc_S_spi_40013000_FULL_NAME_TOKEN spi_40013000
#define DT_N_S_soc_S_spi_40013000_FULL_NAME_UPPER_TOKEN SPI_40013000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40013000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40013000_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_40013000_NODELABEL_NUM 2
#define DT_N_S_soc_S_spi_40013000_FOREACH_NODELABEL(fn) fn(spi1) fn(arduino_spi)
#define DT_N_S_soc_S_spi_40013000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi1, __VA_ARGS__) fn(arduino_spi, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40013000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40013000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_40013000_HASH q04f3jPcynKDa_9eKR_V34RQn5SAL2iX4yHIC7XGkLs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40013000_ORD 94
#define DT_N_S_soc_S_spi_40013000_ORD_STR_SORTABLE 00094

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40013000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	90, /* /soc/pin-controller@48000000/gpio@48000400 */ \
	91, /* /soc/pin-controller@48000000/spi1_miso_pa6 */ \
	92, /* /soc/pin-controller@48000000/spi1_mosi_pa7 */ \
	93, /* /soc/pin-controller@48000000/spi1_sck_pa5 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40013000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40013000_EXISTS 1
#define DT_N_INST_0_st_stm32_spi_fifo DT_N_S_soc_S_spi_40013000
#define DT_N_INST_0_st_stm32_spi      DT_N_S_soc_S_spi_40013000
#define DT_N_NODELABEL_spi1           DT_N_S_soc_S_spi_40013000
#define DT_N_NODELABEL_arduino_spi    DT_N_S_soc_S_spi_40013000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40013000_REG_NUM 1
#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 /* 0x40013000 */
#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_40013000, 0)
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, 0)
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40013000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40013000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40013000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_MATCHES_st_stm32_spi_fifo 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40013000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_MODEL_IDX_0 "stm32-spi-fifo"
#define DT_N_S_soc_S_spi_40013000_COMPAT_MATCHES_st_stm32_spi 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_VENDOR_IDX_1 "STMicroelectronics"
#define DT_N_S_soc_S_spi_40013000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_COMPAT_MODEL_IDX_1 "stm32-spi"
#define DT_N_S_soc_S_spi_40013000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NUM 1
#define DT_N_S_soc_S_spi_40013000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40013000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6
#define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_2_PH DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40013000_P_reg {1073819648 /* 0x40013000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0 1073819648
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_spi_40013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_interrupts {35 /* 0x23 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_40013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_LEN 3
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_ioswp 0
#define DT_N_S_soc_S_spi_40013000_P_ioswp_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width "full-4-to-16-bit"
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_STRING_UNQUOTED full-4-to-16-bit
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_STRING_TOKEN full_4_to_16_bit
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_STRING_UPPER_TOKEN FULL_4_TO_16_BIT
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0 "full-4-to-16-bit"
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_IDX_0_ENUM_VAL_full_4_to_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_ENUM_VAL_full_4_to_16_bit_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, st_spi_data_width, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_st_spi_data_width_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_st_soft_nss 0
#define DT_N_S_soc_S_spi_40013000_P_st_soft_nss_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_pin 6
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_flags 17
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, flags)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, flags)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status "okay"
#define DT_N_S_soc_S_spi_40013000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_40013000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_40013000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, status, 0)
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, status, 0)
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_status_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_compatible {"st,stm32-spi-fifo", "st,stm32-spi"}
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0 "st,stm32-spi-fifo"
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-spi-fifo
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_TOKEN st_stm32_spi_fifo
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1 "st,stm32-spi"
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi
#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, compatible, 0) \
	fn(DT_N_S_soc_S_spi_40013000, compatible, 1)
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, compatible, 1)
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40013000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_compatible_LEN 2
#define DT_N_S_soc_S_spi_40013000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bits 4096
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40013000, clocks, 0, bits)
#define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, clocks, 0)
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, clocks, 0)
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40013000_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_40013000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_dma_coherent 0
#define DT_N_S_soc_S_spi_40013000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40013000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40013000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 *
 * Binding (compatible = arm,armv7m-systick):
 *   $ZEPHYR_BASE/dts/bindings/timer/arm,armv7m-systick.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010"
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UNQUOTED timer@e000e010
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_TOKEN timer_e000e010
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UPPER_TOKEN TIMER_E000E010

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timer_e000e010_NODELABEL_NUM 1
#define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL(fn) fn(systick)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_NODELABEL_VARGS(fn, ...) fn(systick, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM 0
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timer_e000e010_HASH aZrzPLAIRgEwRZJIvTCzJONA6gPgc4QlhkiU5oWGArA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 95
#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00095

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv7m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG(fn) fn(DT_N_S_soc_S_timer_e000e010, 0)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, 0)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_IRQ_LEVEL 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv7m_systick 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv7m-systick"
#define DT_N_S_soc_S_timer_e000e010_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_external_clock_source 0
#define DT_N_S_soc_S_timer_e000e010_P_external_clock_source_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv7m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv7m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv7m-systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv7m_systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV7M_SYSTICK
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_dma_coherent 0
#define DT_N_S_soc_S_timer_e000e010_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40007c00
 *
 * Node identifier: DT_N_S_soc_S_timers_40007c00
 *
 * Binding (compatible = st,stm32-lptim):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-lptim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40007c00_PATH "/soc/timers@40007c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40007c00_FULL_NAME "timers@40007c00"
#define DT_N_S_soc_S_timers_40007c00_FULL_NAME_UNQUOTED timers@40007c00
#define DT_N_S_soc_S_timers_40007c00_FULL_NAME_TOKEN timers_40007c00
#define DT_N_S_soc_S_timers_40007c00_FULL_NAME_UPPER_TOKEN TIMERS_40007C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40007c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40007c00_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40007c00_NODELABEL_NUM 2
#define DT_N_S_soc_S_timers_40007c00_FOREACH_NODELABEL(fn) fn(lptim1) fn(stm32_lp_tick_source)
#define DT_N_S_soc_S_timers_40007c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(lptim1, __VA_ARGS__) fn(stm32_lp_tick_source, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40007c00_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40007c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40007c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40007c00_HASH 0ZbuCp5mjhw6Ls5w9wnMv4hCgy9r4pkUnOw3zpBV8fk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40007c00_ORD 96
#define DT_N_S_soc_S_timers_40007c00_ORD_STR_SORTABLE 00096

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40007c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40007c00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40007c00_EXISTS 1
#define DT_N_INST_0_st_stm32_lptim          DT_N_S_soc_S_timers_40007c00
#define DT_N_NODELABEL_lptim1               DT_N_S_soc_S_timers_40007c00
#define DT_N_NODELABEL_stm32_lp_tick_source DT_N_S_soc_S_timers_40007c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40007c00_REG_NUM 1
#define DT_N_S_soc_S_timers_40007c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_REG_IDX_0_VAL_ADDRESS 1073773568 /* 0x40007c00 */
#define DT_N_S_soc_S_timers_40007c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40007c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40007c00, 0)
#define DT_N_S_soc_S_timers_40007c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, 0)
#define DT_N_S_soc_S_timers_40007c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40007c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40007c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40007c00_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_VAL_irq 49
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40007c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_NAME_wakeup_VAL_irq DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40007c00_IRQ_NAME_wakeup_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_NAME_wakeup_VAL_priority DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40007c00_IRQ_NAME_wakeup_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_IRQ_NAME_wakeup_CONTROLLER DT_N_S_soc_S_timers_40007c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40007c00_COMPAT_MATCHES_st_stm32_lptim 1
#define DT_N_S_soc_S_timers_40007c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40007c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_COMPAT_MODEL_IDX_0 "stm32-lptim"
#define DT_N_S_soc_S_timers_40007c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40007c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40007c00_P_st_prescaler 1
#define DT_N_S_soc_S_timers_40007c00_P_st_prescaler_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40007c00_P_st_prescaler_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_st_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_st_prescaler_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_reg {1073773568 /* 0x40007c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40007c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_reg_IDX_0 1073773568
#define DT_N_S_soc_S_timers_40007c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40007c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_VAL_bits 2147483648
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40007c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_VAL_bus 2
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_VAL_bits 53608584
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40007c00, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40007c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40007c00, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 1)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 1)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40007c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40007c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40007c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_VAL_id 1823
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40007c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40007c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40007c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40007c00, resets, 0)
#define DT_N_S_soc_S_timers_40007c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, resets, 0)
#define DT_N_S_soc_S_timers_40007c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40007c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40007c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40007c00_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_status "okay"
#define DT_N_S_soc_S_timers_40007c00_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_timers_40007c00_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_timers_40007c00_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_timers_40007c00_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_timers_40007c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40007c00_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40007c00, status, 0)
#define DT_N_S_soc_S_timers_40007c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, status, 0)
#define DT_N_S_soc_S_timers_40007c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40007c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_status_LEN 1
#define DT_N_S_soc_S_timers_40007c00_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_compatible {"st,stm32-lptim"}
#define DT_N_S_soc_S_timers_40007c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_compatible_IDX_0 "st,stm32-lptim"
#define DT_N_S_soc_S_timers_40007c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lptim
#define DT_N_S_soc_S_timers_40007c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_lptim
#define DT_N_S_soc_S_timers_40007c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LPTIM
#define DT_N_S_soc_S_timers_40007c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40007c00, compatible, 0)
#define DT_N_S_soc_S_timers_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, compatible, 0)
#define DT_N_S_soc_S_timers_40007c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40007c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40007c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_interrupts {49 /* 0x31 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40007c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_interrupts_IDX_0 49
#define DT_N_S_soc_S_timers_40007c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40007c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names {"wakeup"}
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_IDX_0 "wakeup"
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_IDX_0_STRING_UNQUOTED wakeup
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_IDX_0_STRING_TOKEN wakeup
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN WAKEUP
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40007c00, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40007c00, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40007c00, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40007c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40007c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40007c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40007c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40007c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40007c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/ucpd@4000a000
 *
 * Node identifier: DT_N_S_soc_S_ucpd_4000a000
 *
 * Binding (compatible = st,stm32-ucpd):
 *   $ZEPHYR_BASE/dts/bindings/tcpc/st,stm32-ucpd.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ucpd_4000a000_PATH "/soc/ucpd@4000a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ucpd_4000a000_FULL_NAME "ucpd@4000a000"
#define DT_N_S_soc_S_ucpd_4000a000_FULL_NAME_UNQUOTED ucpd@4000a000
#define DT_N_S_soc_S_ucpd_4000a000_FULL_NAME_TOKEN ucpd_4000a000
#define DT_N_S_soc_S_ucpd_4000a000_FULL_NAME_UPPER_TOKEN UCPD_4000A000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ucpd_4000a000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ucpd_4000a000_CHILD_IDX 41

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ucpd_4000a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_NODELABEL(fn) fn(ucpd1)
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ucpd1, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ucpd_4000a000_CHILD_NUM 0
#define DT_N_S_soc_S_ucpd_4000a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_ucpd_4000a000_HASH dz71PmBvjUI3KHlHmLFqfpqTyoYXdlXBj5AwJKyEJlk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ucpd_4000a000_ORD 97
#define DT_N_S_soc_S_ucpd_4000a000_ORD_STR_SORTABLE 00097

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ucpd_4000a000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ucpd_4000a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ucpd_4000a000_EXISTS 1
#define DT_N_INST_0_st_stm32_ucpd DT_N_S_soc_S_ucpd_4000a000
#define DT_N_NODELABEL_ucpd1      DT_N_S_soc_S_ucpd_4000a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ucpd_4000a000_REG_NUM 1
#define DT_N_S_soc_S_ucpd_4000a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_REG_IDX_0_VAL_ADDRESS 1073782784 /* 0x4000a000 */
#define DT_N_S_soc_S_ucpd_4000a000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_REG(fn) fn(DT_N_S_soc_S_ucpd_4000a000, 0)
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_ucpd_4000a000, 0)
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_ucpd_4000a000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ucpd_4000a000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_RANGES_NUM 0
#define DT_N_S_soc_S_ucpd_4000a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_NUM 1
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_VAL_irq 63
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_ucpd_4000a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_ucpd_4000a000_COMPAT_MATCHES_st_stm32_ucpd 1
#define DT_N_S_soc_S_ucpd_4000a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_ucpd_4000a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_COMPAT_MODEL_IDX_0 "stm32-ucpd"
#define DT_N_S_soc_S_ucpd_4000a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ucpd_4000a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ucpd_4000a000_P_reg {1073782784 /* 0x4000a000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_ucpd_4000a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_reg_IDX_0 1073782784
#define DT_N_S_soc_S_ucpd_4000a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_ucpd_4000a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_VAL_bits 16
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0, bits)
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0, bits)
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0)
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0)
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ucpd_4000a000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_LEN 1
#define DT_N_S_soc_S_ucpd_4000a000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_interrupts {63 /* 0x3f */, 0 /* 0x0 */}
#define DT_N_S_soc_S_ucpd_4000a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_interrupts_IDX_0 63
#define DT_N_S_soc_S_ucpd_4000a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_ucpd_4000a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_psc_ucpdclk 2
#define DT_N_S_soc_S_ucpd_4000a000_P_psc_ucpdclk_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_ucpd_4000a000_P_psc_ucpdclk_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_psc_ucpdclk_IDX_0_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_psc_ucpdclk_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_psc_ucpdclk_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_ifrgap 17
#define DT_N_S_soc_S_ucpd_4000a000_P_ifrgap_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_transwin 8
#define DT_N_S_soc_S_ucpd_4000a000_P_transwin_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_hbitclkdiv 14
#define DT_N_S_soc_S_ucpd_4000a000_P_hbitclkdiv_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_dead_battery 0
#define DT_N_S_soc_S_ucpd_4000a000_P_dead_battery_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_status "disabled"
#define DT_N_S_soc_S_ucpd_4000a000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_ucpd_4000a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_ucpd_4000a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_ucpd_4000a000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_ucpd_4000a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_ucpd_4000a000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ucpd_4000a000, status, 0)
#define DT_N_S_soc_S_ucpd_4000a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ucpd_4000a000, status, 0)
#define DT_N_S_soc_S_ucpd_4000a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ucpd_4000a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ucpd_4000a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_P_status_LEN 1
#define DT_N_S_soc_S_ucpd_4000a000_P_status_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible {"st,stm32-ucpd"}
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_IDX_0 "st,stm32-ucpd"
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-ucpd
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_IDX_0_STRING_TOKEN st_stm32_ucpd
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UCPD
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ucpd_4000a000, compatible, 0)
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ucpd_4000a000, compatible, 0)
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ucpd_4000a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ucpd_4000a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_LEN 1
#define DT_N_S_soc_S_ucpd_4000a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_dma_coherent 0
#define DT_N_S_soc_S_ucpd_4000a000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ucpd_4000a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_wakeup_source 0
#define DT_N_S_soc_S_ucpd_4000a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ucpd_4000a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ucpd_4000a000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /usbphy
 *
 * Node identifier: DT_N_S_usbphy
 *
 * Binding (compatible = usb-nop-xceiv):
 *   $ZEPHYR_BASE/dts/bindings/phy/usb-nop-xceiv.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_usbphy_PATH "/usbphy"

/* Node's name with unit-address: */
#define DT_N_S_usbphy_FULL_NAME "usbphy"
#define DT_N_S_usbphy_FULL_NAME_UNQUOTED usbphy
#define DT_N_S_usbphy_FULL_NAME_TOKEN usbphy
#define DT_N_S_usbphy_FULL_NAME_UPPER_TOKEN USBPHY

/* Node parent (/) identifier: */
#define DT_N_S_usbphy_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_usbphy_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_usbphy_NODELABEL_NUM 1
#define DT_N_S_usbphy_FOREACH_NODELABEL(fn) fn(usb_fs_phy)
#define DT_N_S_usbphy_FOREACH_NODELABEL_VARGS(fn, ...) fn(usb_fs_phy, __VA_ARGS__)
#define DT_N_S_usbphy_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_usbphy_CHILD_NUM 0
#define DT_N_S_usbphy_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_usbphy_FOREACH_CHILD(fn) 
#define DT_N_S_usbphy_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_usbphy_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_usbphy_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_usbphy_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_usbphy_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_usbphy_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_usbphy_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_usbphy_HASH E_X5Gkg3DeUJ3IGdQ884eo5YhX8B_NNNcL9cTxe39SI

/* Node's dependency ordinal: */
#define DT_N_S_usbphy_ORD 98
#define DT_N_S_usbphy_ORD_STR_SORTABLE 00098

/* Ordinals for what this node depends on directly: */
#define DT_N_S_usbphy_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_usbphy_SUPPORTS_ORDS \
	99, /* /soc/usb@40005c00 */

/* Existence and alternate IDs: */
#define DT_N_S_usbphy_EXISTS 1
#define DT_N_INST_0_usb_nop_xceiv DT_N_S_usbphy
#define DT_N_NODELABEL_usb_fs_phy DT_N_S_usbphy

/* Macros for properties that are special in the specification: */
#define DT_N_S_usbphy_REG_NUM 0
#define DT_N_S_usbphy_FOREACH_REG(fn) 
#define DT_N_S_usbphy_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_usbphy_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_usbphy_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_usbphy_RANGES_NUM 0
#define DT_N_S_usbphy_FOREACH_RANGE(fn) 
#define DT_N_S_usbphy_IRQ_NUM 0
#define DT_N_S_usbphy_IRQ_LEVEL 0
#define DT_N_S_usbphy_COMPAT_MATCHES_usb_nop_xceiv 1
#define DT_N_S_usbphy_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_usbphy_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_usbphy_P_compatible {"usb-nop-xceiv"}
#define DT_N_S_usbphy_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_usbphy_P_compatible_IDX_0 "usb-nop-xceiv"
#define DT_N_S_usbphy_P_compatible_IDX_0_STRING_UNQUOTED usb-nop-xceiv
#define DT_N_S_usbphy_P_compatible_IDX_0_STRING_TOKEN usb_nop_xceiv
#define DT_N_S_usbphy_P_compatible_IDX_0_STRING_UPPER_TOKEN USB_NOP_XCEIV
#define DT_N_S_usbphy_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_usbphy, compatible, 0)
#define DT_N_S_usbphy_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_usbphy, compatible, 0)
#define DT_N_S_usbphy_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_usbphy, compatible, 0, __VA_ARGS__)
#define DT_N_S_usbphy_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_usbphy, compatible, 0, __VA_ARGS__)
#define DT_N_S_usbphy_P_compatible_LEN 1
#define DT_N_S_usbphy_P_compatible_EXISTS 1
#define DT_N_S_usbphy_P_dma_coherent 0
#define DT_N_S_usbphy_P_dma_coherent_EXISTS 1
#define DT_N_S_usbphy_P_zephyr_deferred_init 0
#define DT_N_S_usbphy_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_usbphy_P_wakeup_source 0
#define DT_N_S_usbphy_P_wakeup_source_EXISTS 1
#define DT_N_S_usbphy_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_usbphy_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/usb@40005c00
 *
 * Node identifier: DT_N_S_soc_S_usb_40005c00
 *
 * Binding (compatible = st,stm32-usb):
 *   $ZEPHYR_BASE/dts/bindings/usb/st,stm32-usb.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_usb_40005c00_PATH "/soc/usb@40005c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_usb_40005c00_FULL_NAME "usb@40005c00"
#define DT_N_S_soc_S_usb_40005c00_FULL_NAME_UNQUOTED usb@40005c00
#define DT_N_S_soc_S_usb_40005c00_FULL_NAME_TOKEN usb_40005c00
#define DT_N_S_soc_S_usb_40005c00_FULL_NAME_UPPER_TOKEN USB_40005C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_usb_40005c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_usb_40005c00_CHILD_IDX 37

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_usb_40005c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_usb_40005c00_FOREACH_NODELABEL(fn) fn(usb)
#define DT_N_S_soc_S_usb_40005c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(usb, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_usb_40005c00_CHILD_NUM 0
#define DT_N_S_soc_S_usb_40005c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_40005c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_usb_40005c00_HASH 80xV1Zo9Nb21_13c9S9_bF8QGZR2Fp7zcRZfGeZahl0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_usb_40005c00_ORD 99
#define DT_N_S_soc_S_usb_40005c00_ORD_STR_SORTABLE 00099

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_usb_40005c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	98, /* /usbphy */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_usb_40005c00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_usb_40005c00_EXISTS 1
#define DT_N_INST_0_st_stm32_usb DT_N_S_soc_S_usb_40005c00
#define DT_N_NODELABEL_usb       DT_N_S_soc_S_usb_40005c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_usb_40005c00_REG_NUM 1
#define DT_N_S_soc_S_usb_40005c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_REG_IDX_0_VAL_ADDRESS 1073765376 /* 0x40005c00 */
#define DT_N_S_soc_S_usb_40005c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_usb_40005c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_usb_40005c00, 0)
#define DT_N_S_soc_S_usb_40005c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, 0)
#define DT_N_S_soc_S_usb_40005c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_RANGES_NUM 0
#define DT_N_S_soc_S_usb_40005c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_usb_40005c00_IRQ_NUM 2
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_VAL_irq 19
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usb_40005c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usb_VAL_irq DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usb_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usb_VAL_priority DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usb_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usb_CONTROLLER DT_N_S_soc_S_usb_40005c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usbhp_VAL_irq DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usbhp_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usbhp_VAL_priority DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usbhp_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_IRQ_NAME_usbhp_CONTROLLER DT_N_S_soc_S_usb_40005c00_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_usb_40005c00_COMPAT_MATCHES_st_stm32_usb 1
#define DT_N_S_soc_S_usb_40005c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_usb_40005c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_COMPAT_MODEL_IDX_0 "stm32-usb"
#define DT_N_S_soc_S_usb_40005c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_usb_40005c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_usb_40005c00_P_reg {1073765376 /* 0x40005c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_usb_40005c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_reg_IDX_0 1073765376
#define DT_N_S_soc_S_usb_40005c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_usb_40005c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupts {20 /* 0x14 */, 0 /* 0x0 */, 19 /* 0x13 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_2 19
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_usb_40005c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_ram_size 1024
#define DT_N_S_soc_S_usb_40005c00_P_ram_size_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_phys DT_N_S_usbphy
#define DT_N_S_soc_S_usb_40005c00_P_phys_IDX_0 DT_N_S_usbphy
#define DT_N_S_soc_S_usb_40005c00_P_phys_IDX_0_PH DT_N_S_usbphy
#define DT_N_S_soc_S_usb_40005c00_P_phys_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40005c00, phys, 0)
#define DT_N_S_soc_S_usb_40005c00_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, phys, 0)
#define DT_N_S_soc_S_usb_40005c00_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, phys, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, phys, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_phys_LEN 1
#define DT_N_S_soc_S_usb_40005c00_P_phys_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_VAL_bits 8388608
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_40005c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 0, bits)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 0, bits)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_VAL_bus 5
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_VAL_bits 3801224
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_40005c00, clocks, 1, bus) \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 1, bits)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 1, bits)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_usb_40005c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40005c00, clocks, 0) \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 1)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 1)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40005c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_clocks_LEN 2
#define DT_N_S_soc_S_usb_40005c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_num_bidir_endpoints 8
#define DT_N_S_soc_S_usb_40005c00_P_num_bidir_endpoints_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed "full-speed"
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_STRING_UNQUOTED full-speed
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_STRING_TOKEN full_speed
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_STRING_UPPER_TOKEN FULL_SPEED
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_IDX_0 "full-speed"
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_IDX_0_ENUM_VAL_full_speed_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_ENUM_VAL_full_speed_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40005c00, maximum_speed, 0)
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, maximum_speed, 0)
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, maximum_speed, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, maximum_speed, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_LEN 1
#define DT_N_S_soc_S_usb_40005c00_P_maximum_speed_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_status "disabled"
#define DT_N_S_soc_S_usb_40005c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_usb_40005c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_usb_40005c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_usb_40005c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_usb_40005c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_usb_40005c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40005c00, status, 0)
#define DT_N_S_soc_S_usb_40005c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, status, 0)
#define DT_N_S_soc_S_usb_40005c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_status_LEN 1
#define DT_N_S_soc_S_usb_40005c00_P_status_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_compatible {"st,stm32-usb"}
#define DT_N_S_soc_S_usb_40005c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_compatible_IDX_0 "st,stm32-usb"
#define DT_N_S_soc_S_usb_40005c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usb
#define DT_N_S_soc_S_usb_40005c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_usb
#define DT_N_S_soc_S_usb_40005c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USB
#define DT_N_S_soc_S_usb_40005c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40005c00, compatible, 0)
#define DT_N_S_soc_S_usb_40005c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, compatible, 0)
#define DT_N_S_soc_S_usb_40005c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_compatible_LEN 1
#define DT_N_S_soc_S_usb_40005c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names {"usb", "usbhp"}
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_0 "usb"
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_0_STRING_UNQUOTED usb
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_0_STRING_TOKEN usb
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN USB
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_1 "usbhp"
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_1_STRING_UNQUOTED usbhp
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_1_STRING_TOKEN usbhp
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN USBHP
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 0) \
	fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 1)
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 1)
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_40005c00, interrupt_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_LEN 2
#define DT_N_S_soc_S_usb_40005c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_dma_coherent 0
#define DT_N_S_soc_S_usb_40005c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_usb_40005c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_wakeup_source 0
#define DT_N_S_soc_S_usb_40005c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_usb_40005c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_usb_40005c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@40002c00
 *
 * Node identifier: DT_N_S_soc_S_watchdog_40002c00
 *
 * Binding (compatible = st,stm32-window-watchdog):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/st,stm32-window-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_40002c00_PATH "/soc/watchdog@40002c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME "watchdog@40002c00"
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME_UNQUOTED watchdog@40002c00
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME_TOKEN watchdog_40002c00
#define DT_N_S_soc_S_watchdog_40002c00_FULL_NAME_UPPER_TOKEN WATCHDOG_40002C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_40002c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_40002c00_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_watchdog_40002c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_NODELABEL(fn) fn(wwdg)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(wwdg, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_40002c00_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_40002c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_watchdog_40002c00_HASH NKEpaR6mtDKOWUZ_R2tC3uFejChIy267XTRT9LC__CA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_40002c00_ORD 100
#define DT_N_S_soc_S_watchdog_40002c00_ORD_STR_SORTABLE 00100

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_40002c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_40002c00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_40002c00_EXISTS 1
#define DT_N_INST_0_st_stm32_window_watchdog DT_N_S_soc_S_watchdog_40002c00
#define DT_N_NODELABEL_wwdg                  DT_N_S_soc_S_watchdog_40002c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_40002c00_REG_NUM 1
#define DT_N_S_soc_S_watchdog_40002c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_REG_IDX_0_VAL_ADDRESS 1073753088 /* 0x40002c00 */
#define DT_N_S_soc_S_watchdog_40002c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_watchdog_40002c00, 0)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, 0)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_40002c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_NUM 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_irq 0
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_watchdog_40002c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_MATCHES_st_stm32_window_watchdog 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_COMPAT_MODEL_IDX_0 "stm32-window-watchdog"
#define DT_N_S_soc_S_watchdog_40002c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_40002c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_40002c00_P_reg {1073753088 /* 0x40002c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_0 1073753088
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_watchdog_40002c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bits 2048
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bits)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, bits)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_LEN 1
#define DT_N_S_soc_S_watchdog_40002c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status "disabled"
#define DT_N_S_soc_S_watchdog_40002c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_watchdog_40002c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_watchdog_40002c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_40002c00_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible {"st,stm32-window-watchdog"}
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0 "st,stm32-window-watchdog"
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-window-watchdog
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_window_watchdog
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_WINDOW_WATCHDOG
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40002c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_40002c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts {0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_0 0
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_watchdog_40002c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_dma_coherent 0
#define DT_N_S_soc_S_watchdog_40002c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_40002c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_40002c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@40003000
 *
 * Node identifier: DT_N_S_soc_S_watchdog_40003000
 *
 * Binding (compatible = st,stm32-watchdog):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/st,stm32-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_40003000_PATH "/soc/watchdog@40003000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME "watchdog@40003000"
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME_UNQUOTED watchdog@40003000
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME_TOKEN watchdog_40003000
#define DT_N_S_soc_S_watchdog_40003000_FULL_NAME_UPPER_TOKEN WATCHDOG_40003000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_40003000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_40003000_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_watchdog_40003000_NODELABEL_NUM 1
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_NODELABEL(fn) fn(iwdg)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_NODELABEL_VARGS(fn, ...) fn(iwdg, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_40003000_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_40003000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_watchdog_40003000_HASH ZgrqJ_c2LlWOgbyPiYriITNa7e_ieqQvmB0duI6_QGU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_40003000_ORD 101
#define DT_N_S_soc_S_watchdog_40003000_ORD_STR_SORTABLE 00101

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_40003000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_40003000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_40003000_EXISTS 1
#define DT_N_ALIAS_watchdog0          DT_N_S_soc_S_watchdog_40003000
#define DT_N_INST_0_st_stm32_watchdog DT_N_S_soc_S_watchdog_40003000
#define DT_N_NODELABEL_iwdg           DT_N_S_soc_S_watchdog_40003000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_40003000_REG_NUM 1
#define DT_N_S_soc_S_watchdog_40003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_REG_IDX_0_VAL_ADDRESS 1073754112 /* 0x40003000 */
#define DT_N_S_soc_S_watchdog_40003000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG(fn) fn(DT_N_S_soc_S_watchdog_40003000, 0)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40003000, 0)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40003000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_40003000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_40003000_IRQ_NUM 0
#define DT_N_S_soc_S_watchdog_40003000_IRQ_LEVEL 0
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_MATCHES_st_stm32_watchdog 1
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_COMPAT_MODEL_IDX_0 "stm32-watchdog"
#define DT_N_S_soc_S_watchdog_40003000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_40003000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_40003000_P_reg {1073754112 /* 0x40003000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_0 1073754112
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_watchdog_40003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status "okay"
#define DT_N_S_soc_S_watchdog_40003000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_watchdog_40003000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_watchdog_40003000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_watchdog_40003000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40003000, status, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40003000, status, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_40003000_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_compatible {"st,stm32-watchdog"}
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0 "st,stm32-watchdog"
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-watchdog
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_STRING_TOKEN st_stm32_watchdog
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_WATCHDOG
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_40003000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_dma_coherent 0
#define DT_N_S_soc_S_watchdog_40003000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_40003000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_40003000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@1fff7000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000
 *
 * Binding (compatible = st,stm32-nvm-otp):
 *   $ZEPHYR_BASE/dts/bindings/otp/st,stm32-nvm-otp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_PATH "/soc/flash-controller@40022000/flash@1fff7000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FULL_NAME "flash@1fff7000"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FULL_NAME_UNQUOTED flash@1fff7000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FULL_NAME_TOKEN flash_1fff7000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FULL_NAME_UPPER_TOKEN FLASH_1FFF7000

/* Node parent (/soc/flash-controller@40022000) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_PARENT DT_N_S_soc_S_flash_controller_40022000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_NODELABEL(fn) fn(st_nvm_user_otp)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_NODELABEL_VARGS(fn, ...) fn(st_nvm_user_otp, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_HASH sts8G9NjmJGhAnV0DhAjkjCpzKJE1fwLSeGkRlUjYnk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_ORD 102
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_ORD_STR_SORTABLE 00102

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_REQUIRES_ORDS \
	11, /* /soc/flash-controller@40022000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_EXISTS 1
#define DT_N_INST_1_st_stm32_nvm_otp   DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000
#define DT_N_NODELABEL_st_nvm_user_otp DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_REG_IDX_0_VAL_ADDRESS 536834048 /* 0x1fff7000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_COMPAT_MATCHES_st_stm32_nvm_otp 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_COMPAT_MODEL_IDX_0 "stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_reg {536834048 /* 0x1fff7000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_reg_IDX_0 536834048
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status "disabled"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, status, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, status, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_status_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible {"st,stm32-nvm-otp"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_IDX_0 "st,stm32-nvm-otp"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-nvm-otp
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_IDX_0_STRING_TOKEN st_stm32_nvm_otp
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_NVM_OTP
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@8000000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
 *
 * Binding (compatible = st,stm32-nv-flash):
 *   $ZEPHYR_BASE/dts/bindings/mtd/st,stm32-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_PATH "/soc/flash-controller@40022000/flash@8000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FULL_NAME "flash@8000000"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FULL_NAME_UNQUOTED flash@8000000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FULL_NAME_TOKEN flash_8000000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FULL_NAME_UPPER_TOKEN FLASH_8000000

/* Node parent (/soc/flash-controller@40022000) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_PARENT DT_N_S_soc_S_flash_controller_40022000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_NODELABEL(fn) fn(flash0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_HASH jS_k3V146QRc4ZjeAWhuWFk9WTzfrFWauJLjP4fPHoc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_ORD 103
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_ORD_STR_SORTABLE 00103

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_REQUIRES_ORDS \
	11, /* /soc/flash-controller@40022000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_SUPPORTS_ORDS \
	104, /* /soc/flash-controller@40022000/flash@8000000/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_EXISTS 1
#define DT_N_INST_0_st_stm32_nv_flash DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_N_INST_0_soc_nv_flash      DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_N_NODELABEL_flash0         DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_REG_IDX_0_VAL_ADDRESS 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_RANGES_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_RANGES_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_RANGES_IDX_0_VAL_LENGTH 131072 /* 0x20000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_FOREACH_RANGE(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_COMPAT_MATCHES_st_stm32_nv_flash 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_COMPAT_MODEL_IDX_0 "stm32-nv-flash"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_max_erase_time 25
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_max_erase_time_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_erase_block_size 2048
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_write_block_size 8
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_write_block_size_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible {"st,stm32-nv-flash", "soc-nv-flash"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_0 "st,stm32-nv-flash"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-nv-flash
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_nv_flash
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_NV_FLASH
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_1 "soc-nv-flash"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_1_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_1_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_IDX_1_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 0) \
	fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 1)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 1)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_LEN 2
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_reg {134217728 /* 0x8000000 */, 131072 /* 0x20000 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_reg_IDX_0 134217728
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_reg_IDX_1 131072
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@8000000/partitions
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_PATH "/soc/flash-controller@40022000/flash@8000000/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FULL_NAME "partitions"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FULL_NAME_UNQUOTED partitions
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FULL_NAME_TOKEN partitions
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FULL_NAME_UPPER_TOKEN PARTITIONS

/* Node parent (/soc/flash-controller@40022000/flash@8000000) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_NUM 4
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134217728 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134252544 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134301696 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_CHILD_UNIT_ADDR_INT_134344704 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_HASH r8CF6c7oNqk__u_6kUfBaNdcHX6X_OrDziksYhz5Oa8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_ORD 104
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_ORD_STR_SORTABLE 00104

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_REQUIRES_ORDS \
	103, /* /soc/flash-controller@40022000/flash@8000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_SUPPORTS_ORDS \
	105, /* /soc/flash-controller@40022000/flash@8000000/partitions/partition@0 */ \
	106, /* /soc/flash-controller@40022000/flash@8000000/partitions/partition@8800 */ \
	107, /* /soc/flash-controller@40022000/flash@8000000/partitions/partition@14800 */ \
	108, /* /soc/flash-controller@40022000/flash@8000000/partitions/partition@1f000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_REG(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@8000000/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE/dts/bindings/mtd/zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_PATH "/soc/flash-controller@40022000/flash@8000000/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME "partition@0"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_UNQUOTED partition@0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_TOKEN partition_0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_UPPER_TOKEN PARTITION_0

/* Node parent (/soc/flash-controller@40022000/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_HASH 6Sz_ccJ7CngkhSQocJdPkgtWcUey_vlut6fL5MN_ryM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_ORD 105
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00105

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_REQUIRES_ORDS \
	104, /* /soc/flash-controller@40022000/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_EXISTS 1
#define DT_N_INST_0_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0
#define DT_N_NODELABEL_boot_partition       DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 34816 /* 0x8800 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 34816 /* 0x8800 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1 34816
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@8000000/partitions/partition@8800
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE/dts/bindings/mtd/zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_PATH "/soc/flash-controller@40022000/flash@8000000/partitions/partition@8800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FULL_NAME "partition@8800"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FULL_NAME_UNQUOTED partition@8800
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FULL_NAME_TOKEN partition_8800
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FULL_NAME_UPPER_TOKEN PARTITION_8800

/* Node parent (/soc/flash-controller@40022000/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_NODELABEL(fn) fn(slot0_partition)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_HASH 0NSLNPI_C5J7e0rJjg6WAF3To89lVfkTnSaSPvForgM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_ORD 106
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_ORD_STR_SORTABLE 00106

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_REQUIRES_ORDS \
	104, /* /soc/flash-controller@40022000/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_EXISTS 1
#define DT_N_INST_1_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800
#define DT_N_NODELABEL_slot0_partition      DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_REG_IDX_0_VAL_ADDRESS 134252544 /* 0x8008800 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_REG_IDX_0_VAL_SIZE 49152 /* 0xc000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label "image-0"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_STRING_UNQUOTED image-0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_STRING_TOKEN image_0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_STRING_UPPER_TOKEN IMAGE_0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_IDX_0 "image-0"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_reg {34816 /* 0x8800 */, 49152 /* 0xc000 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_reg_IDX_0 34816
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_reg_IDX_1 49152
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@8000000/partitions/partition@14800
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE/dts/bindings/mtd/zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_PATH "/soc/flash-controller@40022000/flash@8000000/partitions/partition@14800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FULL_NAME "partition@14800"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FULL_NAME_UNQUOTED partition@14800
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FULL_NAME_TOKEN partition_14800
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FULL_NAME_UPPER_TOKEN PARTITION_14800

/* Node parent (/soc/flash-controller@40022000/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_NODELABEL(fn) fn(slot1_partition)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_HASH fFEnG7KMLrlsRwn5u3cXyqdGR2D26veT9a0cMctkJBc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_ORD 107
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_ORD_STR_SORTABLE 00107

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_REQUIRES_ORDS \
	104, /* /soc/flash-controller@40022000/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_EXISTS 1
#define DT_N_INST_2_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800
#define DT_N_NODELABEL_slot1_partition      DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_REG_IDX_0_VAL_ADDRESS 134301696 /* 0x8014800 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_REG_IDX_0_VAL_SIZE 43008 /* 0xa800 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label "image-1"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_STRING_UNQUOTED image-1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_STRING_TOKEN image_1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_STRING_UPPER_TOKEN IMAGE_1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_IDX_0 "image-1"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_reg {83968 /* 0x14800 */, 43008 /* 0xa800 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_reg_IDX_0 83968
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_reg_IDX_1 43008
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@40022000/flash@8000000/partitions/partition@1f000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000
 *
 * Binding (compatible = zephyr,mapped-partition):
 *   $ZEPHYR_BASE/dts/bindings/mtd/zephyr,mapped-partition.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_PATH "/soc/flash-controller@40022000/flash@8000000/partitions/partition@1f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FULL_NAME "partition@1f000"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FULL_NAME_UNQUOTED partition@1f000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FULL_NAME_TOKEN partition_1f000
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FULL_NAME_UPPER_TOKEN PARTITION_1F000

/* Node parent (/soc/flash-controller@40022000/flash@8000000/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_PARENT DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_NODELABEL(fn) fn(storage_partition)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(storage_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_HASH 9dVwn7PaOgLhrIvdJOzU_LaDxeweWidfPecf57_jiak

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_ORD 108
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_ORD_STR_SORTABLE 00108

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_REQUIRES_ORDS \
	104, /* /soc/flash-controller@40022000/flash@8000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_EXISTS 1
#define DT_N_INST_3_zephyr_mapped_partition DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000
#define DT_N_NODELABEL_storage_partition    DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_REG_IDX_0_VAL_ADDRESS 134344704 /* 0x801f000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_COMPAT_MATCHES_zephyr_mapped_partition 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_COMPAT_MODEL_IDX_0 "mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label "storage"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_STRING_UNQUOTED storage
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_STRING_TOKEN storage
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_STRING_UPPER_TOKEN STORAGE
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_IDX_0 "storage"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, label, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_reg_IDX_0 126976
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible {"zephyr,mapped-partition"}
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_IDX_0 "zephyr,mapped-partition"
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,mapped-partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_IDX_0_STRING_TOKEN zephyr_mapped_partition
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MAPPED_PARTITION
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_dma_coherent 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48000c00
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_PATH "/soc/pin-controller@48000000/gpio@48000c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FULL_NAME "gpio@48000c00"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FULL_NAME_UNQUOTED gpio@48000c00
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FULL_NAME_TOKEN gpio_48000c00
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FULL_NAME_UPPER_TOKEN GPIO_48000C00

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_NODELABEL(fn) fn(gpiod)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiod, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_HASH u2DqKzVc8Kgi9iMl9smjExSHInTly4SN9RvuvIXZQe8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_ORD 109
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_ORD_STR_SORTABLE 00109

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_EXISTS 1
#define DT_N_INST_3_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00
#define DT_N_NODELABEL_gpiod      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_REG_IDX_0_VAL_ADDRESS 1207962624 /* 0x48000c00 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_reg {1207962624 /* 0x48000c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_reg_IDX_0 1207962624
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_VAL_bits 8
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48001000
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_PATH "/soc/pin-controller@48000000/gpio@48001000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FULL_NAME "gpio@48001000"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FULL_NAME_UNQUOTED gpio@48001000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FULL_NAME_TOKEN gpio_48001000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FULL_NAME_UPPER_TOKEN GPIO_48001000

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_NODELABEL(fn) fn(gpioe)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpioe, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_HASH f_fCfYEtBkeaIc2VCMEHUuaNoFMeL3PBB4lEAkfQY50

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_ORD 110
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_ORD_STR_SORTABLE 00110

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_EXISTS 1
#define DT_N_INST_4_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000
#define DT_N_NODELABEL_gpioe      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_REG_IDX_0_VAL_ADDRESS 1207963648 /* 0x48001000 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_reg {1207963648 /* 0x48001000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_reg_IDX_0 1207963648
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_VAL_bits 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48001400
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_PATH "/soc/pin-controller@48000000/gpio@48001400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FULL_NAME "gpio@48001400"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FULL_NAME_UNQUOTED gpio@48001400
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FULL_NAME_TOKEN gpio_48001400
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FULL_NAME_UPPER_TOKEN GPIO_48001400

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_NODELABEL(fn) fn(gpiof)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiof, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_HASH bmSOeZi25YolypCkHDKjLQJ9ODqu57WnBB3t7MFcjqM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_ORD 111
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_ORD_STR_SORTABLE 00111

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_EXISTS 1
#define DT_N_INST_5_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400
#define DT_N_NODELABEL_gpiof      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_REG_IDX_0_VAL_ADDRESS 1207964672 /* 0x48001400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_reg {1207964672 /* 0x48001400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_reg_IDX_0 1207964672
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_VAL_bits 32
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pin-controller@48000000/gpio@48001800
 *
 * Node identifier: DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800
 *
 * Binding (compatible = st,stm32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/st,stm32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_PATH "/soc/pin-controller@48000000/gpio@48001800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FULL_NAME "gpio@48001800"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FULL_NAME_UNQUOTED gpio@48001800
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FULL_NAME_TOKEN gpio_48001800
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FULL_NAME_UPPER_TOKEN GPIO_48001800

/* Node parent (/soc/pin-controller@48000000) identifier: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_PARENT DT_N_S_soc_S_pin_controller_48000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_NODELABEL_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_NODELABEL(fn) fn(gpiog)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpiog, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_CHILD_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_HASH fa9JItnpx2_hWd8DAbfvJcEIMTjV8D3ZTeDufB_vqF0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_ORD 112
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_ORD_STR_SORTABLE 00112

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_REQUIRES_ORDS \
	9, /* /soc/rcc@40021000 */ \
	18, /* /soc/pin-controller@48000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_EXISTS 1
#define DT_N_INST_6_st_stm32_gpio DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800
#define DT_N_NODELABEL_gpiog      DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_REG_NUM 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_REG_IDX_0_VAL_ADDRESS 1207965696 /* 0x48001800 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_REG(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_RANGES_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_IRQ_NUM 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_IRQ_LEVEL 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_COMPAT_MATCHES_st_stm32_gpio 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_COMPAT_MODEL_IDX_0 "stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_reg {1207965696 /* 0x48001800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_reg_IDX_0 1207965696
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_reg_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_VAL_bus 76
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_VAL_bits 64
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0, bits)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_ngpios 16
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_gpio_controller 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible {"st,stm32-gpio"}
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_IDX_0 "st,stm32-gpio"
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, compatible, 0)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_LEN 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_dma_coherent 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_wakeup_source 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_S_counter_PATH "/soc/timers@40000000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000000) identifier: */
#define DT_N_S_soc_S_timers_40000000_S_counter_PARENT DT_N_S_soc_S_timers_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_S_counter_HASH q1HYCxKR_QqakI62hwcbYK3CrWp5E_XbPwXUySU4se8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_S_counter_ORD 113
#define DT_N_S_soc_S_timers_40000000_S_counter_ORD_STR_SORTABLE 00113

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_S_counter_REQUIRES_ORDS \
	47, /* /soc/timers@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_S_counter_EXISTS 1
#define DT_N_INST_1_st_stm32_counter DT_N_S_soc_S_timers_40000000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000000/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000000_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_PATH "/soc/timers@40000000/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000000) identifier: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_PARENT DT_N_S_soc_S_timers_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000000_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_HASH xeDccz_QkMBo6l8_wMCsnsC88OsLpoM_UNpiSWf6rWM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_ORD 114
#define DT_N_S_soc_S_timers_40000000_S_qdec_ORD_STR_SORTABLE 00114

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_REQUIRES_ORDS \
	47, /* /soc/timers@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_EXISTS 1
#define DT_N_INST_1_st_stm32_qdec DT_N_S_soc_S_timers_40000000_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000000_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000000_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000000_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_PATH "/soc/timers@40000400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_FULL_NAME "timers@40000400"
#define DT_N_S_soc_S_timers_40000400_FULL_NAME_UNQUOTED timers@40000400
#define DT_N_S_soc_S_timers_40000400_FULL_NAME_TOKEN timers_40000400
#define DT_N_S_soc_S_timers_40000400_FULL_NAME_UPPER_TOKEN TIMERS_40000400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_CHILD_IDX 27

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000400_FOREACH_NODELABEL(fn) fn(timers3)
#define DT_N_S_soc_S_timers_40000400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_qdec)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_qdec)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_HASH baeUapzy1gNL2E23NOiz9371NQp1G8KhvyeXIcEPqLk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_ORD 115
#define DT_N_S_soc_S_timers_40000400_ORD_STR_SORTABLE 00115

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_SUPPORTS_ORDS \
	116, /* /soc/timers@40000400/counter */ \
	117, /* /soc/timers@40000400/pwm */ \
	118, /* /soc/timers@40000400/qdec */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_EXISTS 1
#define DT_N_INST_2_st_stm32_timers DT_N_S_soc_S_timers_40000400
#define DT_N_NODELABEL_timers3      DT_N_S_soc_S_timers_40000400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_REG_NUM 1
#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_ADDRESS 1073742848 /* 0x40000400 */
#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000400, 0)
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, 0)
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_P_reg {1073742848 /* 0x40000400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0 1073742848
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bus 9
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1)
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1)
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id 1793
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000400, resets, 0, id)
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, resets, 0, id)
#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, resets, 0)
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, resets, 0)
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, status, 0)
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, status, 0)
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupts {29 /* 0x1d */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_S_counter_PATH "/soc/timers@40000400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000400) identifier: */
#define DT_N_S_soc_S_timers_40000400_S_counter_PARENT DT_N_S_soc_S_timers_40000400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_S_counter_HASH JNkHbJAdpxqum04dZjR7ujFGNxo62pj2eB31ikv0Phc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_S_counter_ORD 116
#define DT_N_S_soc_S_timers_40000400_S_counter_ORD_STR_SORTABLE 00116

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_S_counter_REQUIRES_ORDS \
	115, /* /soc/timers@40000400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_S_counter_EXISTS 1
#define DT_N_INST_2_st_stm32_counter DT_N_S_soc_S_timers_40000400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_PATH "/soc/timers@40000400/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000400) identifier: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_PARENT DT_N_S_soc_S_timers_40000400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_HASH 3XEqw4Q0MqUTTpvQ0Yrht2rVkAAPsKyjdgccEVU8gEE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD 117
#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD_STR_SORTABLE 00117

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_REQUIRES_ORDS \
	115, /* /soc/timers@40000400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_EXISTS 1
#define DT_N_INST_2_st_stm32_pwm DT_N_S_soc_S_timers_40000400_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000400_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000400/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000400_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_PATH "/soc/timers@40000400/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000400) identifier: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_PARENT DT_N_S_soc_S_timers_40000400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000400_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_HASH XoYaEyYM5OKvrXAYNQJb_KuMBHYcObyudHjfcpXT8_Q

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_ORD 118
#define DT_N_S_soc_S_timers_40000400_S_qdec_ORD_STR_SORTABLE 00118

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_REQUIRES_ORDS \
	115, /* /soc/timers@40000400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_EXISTS 1
#define DT_N_INST_2_st_stm32_qdec DT_N_S_soc_S_timers_40000400_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000400_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000400_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000400_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_PATH "/soc/timers@40000800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_FULL_NAME "timers@40000800"
#define DT_N_S_soc_S_timers_40000800_FULL_NAME_UNQUOTED timers@40000800
#define DT_N_S_soc_S_timers_40000800_FULL_NAME_TOKEN timers_40000800
#define DT_N_S_soc_S_timers_40000800_FULL_NAME_UPPER_TOKEN TIMERS_40000800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40000800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_CHILD_IDX 28

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40000800_FOREACH_NODELABEL(fn) fn(timers4)
#define DT_N_S_soc_S_timers_40000800_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers4, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40000800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_qdec)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_qdec)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40000800_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_HASH VTBFi6bYiewunKr1vKL59kMmaq2wTI7eroMWbGtK2dw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_ORD 119
#define DT_N_S_soc_S_timers_40000800_ORD_STR_SORTABLE 00119

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_SUPPORTS_ORDS \
	120, /* /soc/timers@40000800/counter */ \
	121, /* /soc/timers@40000800/pwm */ \
	122, /* /soc/timers@40000800/qdec */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_EXISTS 1
#define DT_N_INST_3_st_stm32_timers DT_N_S_soc_S_timers_40000800
#define DT_N_NODELABEL_timers4      DT_N_S_soc_S_timers_40000800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_REG_NUM 1
#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_ADDRESS 1073743872 /* 0x40000800 */
#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40000800, 0)
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, 0)
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40000800_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40000800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40000800_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40000800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40000800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_P_reg {1073743872 /* 0x40000800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0 1073743872
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40000800_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits 4
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bus 9
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1)
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1)
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40000800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40000800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id 1794
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40000800, resets, 0, id)
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, resets, 0, id)
#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, resets, 0)
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, resets, 0)
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40000800_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_countermode 0
#define DT_N_S_soc_S_timers_40000800_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40000800_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, status, 0)
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, status, 0)
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupts {30 /* 0x1e */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40000800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_S_counter_PATH "/soc/timers@40000800/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40000800) identifier: */
#define DT_N_S_soc_S_timers_40000800_S_counter_PARENT DT_N_S_soc_S_timers_40000800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_S_counter_HASH It81r5Kkjm8b1AfJHPW0z0jZ9dof3VW5417OU_gyZtc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_S_counter_ORD 120
#define DT_N_S_soc_S_timers_40000800_S_counter_ORD_STR_SORTABLE 00120

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_S_counter_REQUIRES_ORDS \
	119, /* /soc/timers@40000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_S_counter_EXISTS 1
#define DT_N_INST_3_st_stm32_counter DT_N_S_soc_S_timers_40000800_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40000800_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_PATH "/soc/timers@40000800/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40000800) identifier: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_PARENT DT_N_S_soc_S_timers_40000800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_HASH rmmRd1gBchFTmlpcPkj2kPN2S9h0o7_bVDPViAglyik

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD 121
#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD_STR_SORTABLE 00121

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_REQUIRES_ORDS \
	119, /* /soc/timers@40000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_EXISTS 1
#define DT_N_INST_3_st_stm32_pwm DT_N_S_soc_S_timers_40000800_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40000800_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40000800/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40000800_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_PATH "/soc/timers@40000800/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40000800) identifier: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_PARENT DT_N_S_soc_S_timers_40000800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40000800_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_HASH NyJhopD0plir_yCl3bvK19fzvR7T8hmdf4SgsPGbBRs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_ORD 122
#define DT_N_S_soc_S_timers_40000800_S_qdec_ORD_STR_SORTABLE 00122

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_REQUIRES_ORDS \
	119, /* /soc/timers@40000800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_EXISTS 1
#define DT_N_INST_3_st_stm32_qdec DT_N_S_soc_S_timers_40000800_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40000800_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40000800_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40000800_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001000
 *
 * Node identifier: DT_N_S_soc_S_timers_40001000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001000_PATH "/soc/timers@40001000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001000_FULL_NAME "timers@40001000"
#define DT_N_S_soc_S_timers_40001000_FULL_NAME_UNQUOTED timers@40001000
#define DT_N_S_soc_S_timers_40001000_FULL_NAME_TOKEN timers_40001000
#define DT_N_S_soc_S_timers_40001000_FULL_NAME_UPPER_TOKEN TIMERS_40001000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40001000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001000_CHILD_IDX 29

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40001000_FOREACH_NODELABEL(fn) fn(timers6)
#define DT_N_S_soc_S_timers_40001000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers6, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001000_CHILD_NUM 1
#define DT_N_S_soc_S_timers_40001000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001000_HASH Nsz_iy2H8UvqHZMouFTv3bvFrOuL3LyjaTTN24v0eBQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001000_ORD 123
#define DT_N_S_soc_S_timers_40001000_ORD_STR_SORTABLE 00123

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001000_SUPPORTS_ORDS \
	124, /* /soc/timers@40001000/counter */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001000_EXISTS 1
#define DT_N_INST_4_st_stm32_timers DT_N_S_soc_S_timers_40001000
#define DT_N_NODELABEL_timers6      DT_N_S_soc_S_timers_40001000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001000_REG_NUM 1
#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_ADDRESS 1073745920 /* 0x40001000 */
#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40001000, 0)
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, 0)
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_irq 54
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40001000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40001000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40001000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40001000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40001000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001000_P_reg {1073745920 /* 0x40001000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0 1073745920
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40001000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits 16
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bus 9
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1)
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1)
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40001000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id 1796
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001000, resets, 0, id)
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, resets, 0, id)
#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, resets, 0)
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, resets, 0)
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40001000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40001000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40001000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status "disabled"
#define DT_N_S_soc_S_timers_40001000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, status, 0)
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, status, 0)
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupts {54 /* 0x36 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0 54
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40001000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40001000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001000_S_counter_PATH "/soc/timers@40001000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40001000) identifier: */
#define DT_N_S_soc_S_timers_40001000_S_counter_PARENT DT_N_S_soc_S_timers_40001000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001000_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001000_S_counter_HASH kRqNwCO_GFQ9B_IU80aWEsZniZ2xLsueygEKHK_oRqE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001000_S_counter_ORD 124
#define DT_N_S_soc_S_timers_40001000_S_counter_ORD_STR_SORTABLE 00124

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001000_S_counter_REQUIRES_ORDS \
	123, /* /soc/timers@40001000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001000_S_counter_EXISTS 1
#define DT_N_INST_4_st_stm32_counter DT_N_S_soc_S_timers_40001000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40001000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001400
 *
 * Node identifier: DT_N_S_soc_S_timers_40001400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001400_PATH "/soc/timers@40001400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001400_FULL_NAME "timers@40001400"
#define DT_N_S_soc_S_timers_40001400_FULL_NAME_UNQUOTED timers@40001400
#define DT_N_S_soc_S_timers_40001400_FULL_NAME_TOKEN timers_40001400
#define DT_N_S_soc_S_timers_40001400_FULL_NAME_UPPER_TOKEN TIMERS_40001400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40001400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001400_CHILD_IDX 30

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40001400_FOREACH_NODELABEL(fn) fn(timers7)
#define DT_N_S_soc_S_timers_40001400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers7, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001400_CHILD_NUM 1
#define DT_N_S_soc_S_timers_40001400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001400_HASH NWGZgzDJgqZSuO0DPWROIlkjRWjN3_VzkmbGsEAbECw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001400_ORD 125
#define DT_N_S_soc_S_timers_40001400_ORD_STR_SORTABLE 00125

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001400_SUPPORTS_ORDS \
	126, /* /soc/timers@40001400/counter */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001400_EXISTS 1
#define DT_N_INST_5_st_stm32_timers DT_N_S_soc_S_timers_40001400
#define DT_N_NODELABEL_timers7      DT_N_S_soc_S_timers_40001400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001400_REG_NUM 1
#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_ADDRESS 1073746944 /* 0x40001400 */
#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40001400, 0)
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, 0)
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001400_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_irq 55
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40001400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40001400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40001400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40001400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40001400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001400_P_reg {1073746944 /* 0x40001400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0 1073746944
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40001400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus 88
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits 32
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bus 9
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1)
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1)
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40001400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40001400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id 1797
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40001400, resets, 0, id)
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, resets, 0, id)
#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, resets, 0)
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, resets, 0)
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40001400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40001400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40001400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status "disabled"
#define DT_N_S_soc_S_timers_40001400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, status, 0)
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, status, 0)
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupts {55 /* 0x37 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0 55
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40001400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40001400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40001400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40001400_S_counter_PATH "/soc/timers@40001400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40001400) identifier: */
#define DT_N_S_soc_S_timers_40001400_S_counter_PARENT DT_N_S_soc_S_timers_40001400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40001400_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40001400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40001400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40001400_S_counter_HASH yUMrsaqgcXElOUnLnHc7vIdLGcToiUBEnmAPHwvJ0BA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40001400_S_counter_ORD 126
#define DT_N_S_soc_S_timers_40001400_S_counter_ORD_STR_SORTABLE 00126

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40001400_S_counter_REQUIRES_ORDS \
	125, /* /soc/timers@40001400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40001400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40001400_S_counter_EXISTS 1
#define DT_N_INST_5_st_stm32_counter DT_N_S_soc_S_timers_40001400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40001400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40001400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40001400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40001400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40001400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40001400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40012c00
 *
 * Node identifier: DT_N_S_soc_S_timers_40012c00
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40012c00_PATH "/soc/timers@40012c00"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40012c00_FULL_NAME "timers@40012c00"
#define DT_N_S_soc_S_timers_40012c00_FULL_NAME_UNQUOTED timers@40012c00
#define DT_N_S_soc_S_timers_40012c00_FULL_NAME_TOKEN timers_40012c00
#define DT_N_S_soc_S_timers_40012c00_FULL_NAME_UPPER_TOKEN TIMERS_40012C00

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40012c00_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40012c00_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40012c00_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40012c00_FOREACH_NODELABEL(fn) fn(timers1)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40012c00_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40012c00_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40012c00_S_pwm) fn(DT_N_S_soc_S_timers_40012c00_S_counter) fn(DT_N_S_soc_S_timers_40012c00_S_qdec)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40012c00_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40012c00_S_qdec)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40012c00_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40012c00_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40012c00_HASH 3LegaBe_XYAmus4r7JdPqj5bScAsVFzbsAzhohL9Bqc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40012c00_ORD 127
#define DT_N_S_soc_S_timers_40012c00_ORD_STR_SORTABLE 00127

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40012c00_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40012c00_SUPPORTS_ORDS \
	128, /* /soc/timers@40012c00/counter */ \
	129, /* /soc/timers@40012c00/pwm */ \
	130, /* /soc/timers@40012c00/qdec */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40012c00_EXISTS 1
#define DT_N_INST_1_st_stm32_timers DT_N_S_soc_S_timers_40012c00
#define DT_N_NODELABEL_timers1      DT_N_S_soc_S_timers_40012c00

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40012c00_REG_NUM 1
#define DT_N_S_soc_S_timers_40012c00_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_REG_IDX_0_VAL_ADDRESS 1073818624 /* 0x40012c00 */
#define DT_N_S_soc_S_timers_40012c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40012c00_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40012c00, 0)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, 0)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40012c00_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40012c00_IRQ_NUM 4
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_VAL_irq 25
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_VAL_irq 26
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_VAL_irq 27
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40012c00_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_brk_VAL_irq DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_brk_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_brk_VAL_priority DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_brk_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_brk_CONTROLLER DT_N_S_soc_S_timers_40012c00_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_up_VAL_irq DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_up_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_up_VAL_priority DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_up_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_up_CONTROLLER DT_N_S_soc_S_timers_40012c00_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_trgcom_VAL_irq DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_trgcom_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_trgcom_VAL_priority DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_trgcom_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_trgcom_CONTROLLER DT_N_S_soc_S_timers_40012c00_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_cc_VAL_irq DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_cc_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_cc_VAL_priority DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_cc_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_IRQ_NAME_cc_CONTROLLER DT_N_S_soc_S_timers_40012c00_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_timers_40012c00_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40012c00_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40012c00_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40012c00_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40012c00_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40012c00_P_reg {1073818624 /* 0x40012c00 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40012c00_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_reg_IDX_0 1073818624
#define DT_N_S_soc_S_timers_40012c00_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40012c00_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_VAL_bits 2048
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40012c00, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_VAL_bus 10
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40012c00, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40012c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 1)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 1)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40012c00_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_VAL_id 2059
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40012c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, resets, 0, id)
#define DT_N_S_soc_S_timers_40012c00_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40012c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00, resets, 0)
#define DT_N_S_soc_S_timers_40012c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, resets, 0)
#define DT_N_S_soc_S_timers_40012c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40012c00_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40012c00_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_countermode 0
#define DT_N_S_soc_S_timers_40012c00_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40012c00_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40012c00_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_status "disabled"
#define DT_N_S_soc_S_timers_40012c00_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40012c00_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40012c00_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40012c00_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40012c00_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40012c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00, status, 0)
#define DT_N_S_soc_S_timers_40012c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, status, 0)
#define DT_N_S_soc_S_timers_40012c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_status_LEN 1
#define DT_N_S_soc_S_timers_40012c00_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40012c00_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40012c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40012c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40012c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40012c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40012c00_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */, 25 /* 0x19 */, 0 /* 0x0 */, 26 /* 0x1a */, 0 /* 0x0 */, 27 /* 0x1b */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_2 25
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_4 26
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_6 27
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_timers_40012c00_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names {"brk", "up", "trgcom", "cc"}
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_0 "brk"
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_0_STRING_UNQUOTED brk
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_0_STRING_TOKEN brk
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_1 "up"
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_1_STRING_UNQUOTED up
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_1_STRING_TOKEN up
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_2 "trgcom"
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_2_STRING_TOKEN trgcom
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_3 "cc"
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_3_STRING_UNQUOTED cc
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_3_STRING_TOKEN cc
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 0) \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 1) \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 2) \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40012c00, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_LEN 4
#define DT_N_S_soc_S_timers_40012c00_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40012c00_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40012c00_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40012c00_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40012c00_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40012c00/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40012c00_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_PATH "/soc/timers@40012c00/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40012c00_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40012c00_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40012c00_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40012c00) identifier: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_PARENT DT_N_S_soc_S_timers_40012c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40012c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40012c00_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_HASH kIF7VDJJsNJuGIIuZ11LPstYbZBQN94NsUPmNZqCzHg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_ORD 128
#define DT_N_S_soc_S_timers_40012c00_S_counter_ORD_STR_SORTABLE 00128

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_REQUIRES_ORDS \
	127, /* /soc/timers@40012c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_EXISTS 1
#define DT_N_INST_0_st_stm32_counter DT_N_S_soc_S_timers_40012c00_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40012c00_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40012c00_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40012c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40012c00/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40012c00_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_PATH "/soc/timers@40012c00/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40012c00) identifier: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_PARENT DT_N_S_soc_S_timers_40012c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40012c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_HASH g97nbdWpfWs0szJYsIofhjyur31j3pJteaFY2J9NhwY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_ORD 129
#define DT_N_S_soc_S_timers_40012c00_S_pwm_ORD_STR_SORTABLE 00129

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_REQUIRES_ORDS \
	127, /* /soc/timers@40012c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_EXISTS 1
#define DT_N_INST_1_st_stm32_pwm DT_N_S_soc_S_timers_40012c00_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40012c00_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40012c00_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40012c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40012c00/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40012c00_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_PATH "/soc/timers@40012c00/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40012c00) identifier: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_PARENT DT_N_S_soc_S_timers_40012c00

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40012c00) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_HASH qMdLUemeDTQeykyd3YiCtvWbzpMdNSnqnGUKo4PFw_0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_ORD 130
#define DT_N_S_soc_S_timers_40012c00_S_qdec_ORD_STR_SORTABLE 00130

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_REQUIRES_ORDS \
	127, /* /soc/timers@40012c00 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_EXISTS 1
#define DT_N_INST_0_st_stm32_qdec DT_N_S_soc_S_timers_40012c00_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40012c00_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40012c00_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40012c00_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_filter_level_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_filter_level_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_filter_level_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_filter_level_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40012c00_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40013400
 *
 * Node identifier: DT_N_S_soc_S_timers_40013400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40013400_PATH "/soc/timers@40013400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40013400_FULL_NAME "timers@40013400"
#define DT_N_S_soc_S_timers_40013400_FULL_NAME_UNQUOTED timers@40013400
#define DT_N_S_soc_S_timers_40013400_FULL_NAME_TOKEN timers_40013400
#define DT_N_S_soc_S_timers_40013400_FULL_NAME_UPPER_TOKEN TIMERS_40013400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40013400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40013400_CHILD_IDX 31

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40013400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40013400_FOREACH_NODELABEL(fn) fn(timers8)
#define DT_N_S_soc_S_timers_40013400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers8, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40013400_CHILD_NUM 3
#define DT_N_S_soc_S_timers_40013400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40013400_S_pwm) fn(DT_N_S_soc_S_timers_40013400_S_counter) fn(DT_N_S_soc_S_timers_40013400_S_qdec)
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40013400_S_counter) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40013400_S_qdec)
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40013400_S_counter, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40013400_S_qdec, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40013400_HASH FF_euBmA_AoGdsnKOZTe7TyZCUD7Zw41dsQG3AFr1KM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40013400_ORD 131
#define DT_N_S_soc_S_timers_40013400_ORD_STR_SORTABLE 00131

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40013400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40013400_SUPPORTS_ORDS \
	132, /* /soc/timers@40013400/counter */ \
	133, /* /soc/timers@40013400/pwm */ \
	134, /* /soc/timers@40013400/qdec */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40013400_EXISTS 1
#define DT_N_INST_6_st_stm32_timers DT_N_S_soc_S_timers_40013400
#define DT_N_NODELABEL_timers8      DT_N_S_soc_S_timers_40013400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40013400_REG_NUM 1
#define DT_N_S_soc_S_timers_40013400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_REG_IDX_0_VAL_ADDRESS 1073820672 /* 0x40013400 */
#define DT_N_S_soc_S_timers_40013400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40013400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40013400, 0)
#define DT_N_S_soc_S_timers_40013400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, 0)
#define DT_N_S_soc_S_timers_40013400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40013400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40013400_IRQ_NUM 4
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_VAL_irq 43
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_VAL_irq 44
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_VAL_irq 45
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_VAL_irq 46
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40013400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_brk_VAL_irq DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_brk_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_brk_VAL_priority DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_brk_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_brk_CONTROLLER DT_N_S_soc_S_timers_40013400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_up_VAL_irq DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_VAL_irq
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_up_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_up_VAL_priority DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_VAL_priority
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_up_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_up_CONTROLLER DT_N_S_soc_S_timers_40013400_IRQ_IDX_1_CONTROLLER
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_trgcom_VAL_irq DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_VAL_irq
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_trgcom_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_trgcom_VAL_priority DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_VAL_priority
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_trgcom_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_trgcom_CONTROLLER DT_N_S_soc_S_timers_40013400_IRQ_IDX_2_CONTROLLER
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_cc_VAL_irq DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_VAL_irq
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_cc_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_cc_VAL_priority DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_VAL_priority
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_cc_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_IRQ_NAME_cc_CONTROLLER DT_N_S_soc_S_timers_40013400_IRQ_IDX_3_CONTROLLER
#define DT_N_S_soc_S_timers_40013400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40013400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40013400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40013400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40013400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40013400_P_reg {1073820672 /* 0x40013400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40013400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_reg_IDX_0 1073820672
#define DT_N_S_soc_S_timers_40013400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40013400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_VAL_bits 8192
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40013400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_VAL_bus 10
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40013400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40013400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40013400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 1)
#define DT_N_S_soc_S_timers_40013400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 1)
#define DT_N_S_soc_S_timers_40013400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40013400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_VAL_id 2061
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40013400, resets, 0, id)
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, resets, 0, id)
#define DT_N_S_soc_S_timers_40013400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40013400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400, resets, 0)
#define DT_N_S_soc_S_timers_40013400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, resets, 0)
#define DT_N_S_soc_S_timers_40013400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40013400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40013400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40013400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40013400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40013400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_status "disabled"
#define DT_N_S_soc_S_timers_40013400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40013400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40013400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40013400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40013400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40013400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400, status, 0)
#define DT_N_S_soc_S_timers_40013400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, status, 0)
#define DT_N_S_soc_S_timers_40013400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40013400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40013400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40013400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40013400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40013400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40013400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40013400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts {43 /* 0x2b */, 0 /* 0x0 */, 44 /* 0x2c */, 0 /* 0x0 */, 45 /* 0x2d */, 0 /* 0x0 */, 46 /* 0x2e */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_0 43
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_2 44
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_3 0
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_4 45
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_6 46
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_timers_40013400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names {"brk", "up", "trgcom", "cc"}
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_0 "brk"
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_0_STRING_UNQUOTED brk
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_0_STRING_TOKEN brk
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_1 "up"
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_1_STRING_UNQUOTED up
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_1_STRING_TOKEN up
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_2 "trgcom"
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_2_STRING_TOKEN trgcom
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_3 "cc"
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_3_STRING_UNQUOTED cc
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_3_STRING_TOKEN cc
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 0) \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 1) \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 2) \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 3)
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40013400, interrupt_names, 3, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_LEN 4
#define DT_N_S_soc_S_timers_40013400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40013400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40013400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40013400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40013400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40013400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40013400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40013400_S_counter_PATH "/soc/timers@40013400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40013400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40013400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40013400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40013400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40013400) identifier: */
#define DT_N_S_soc_S_timers_40013400_S_counter_PARENT DT_N_S_soc_S_timers_40013400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40013400_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40013400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40013400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40013400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40013400_S_counter_HASH Uq1ZlAm_aEQzTHrsxOMDcKgcF4MMnupKoZycdaCT7Oc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40013400_S_counter_ORD 132
#define DT_N_S_soc_S_timers_40013400_S_counter_ORD_STR_SORTABLE 00132

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40013400_S_counter_REQUIRES_ORDS \
	131, /* /soc/timers@40013400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40013400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40013400_S_counter_EXISTS 1
#define DT_N_INST_6_st_stm32_counter DT_N_S_soc_S_timers_40013400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40013400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40013400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40013400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40013400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40013400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40013400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40013400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40013400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40013400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40013400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40013400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40013400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40013400/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40013400_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_PATH "/soc/timers@40013400/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40013400_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40013400_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40013400_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40013400) identifier: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_PARENT DT_N_S_soc_S_timers_40013400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40013400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40013400_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_HASH _RxktOOKFZWf2oilmHATi7Qrz3qCO_0xGy1qTQJh3SE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_ORD 133
#define DT_N_S_soc_S_timers_40013400_S_pwm_ORD_STR_SORTABLE 00133

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_REQUIRES_ORDS \
	131, /* /soc/timers@40013400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_EXISTS 1
#define DT_N_INST_4_st_stm32_pwm DT_N_S_soc_S_timers_40013400_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40013400_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40013400_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40013400_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40013400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40013400/qdec
 *
 * Node identifier: DT_N_S_soc_S_timers_40013400_S_qdec
 *
 * Binding (compatible = st,stm32-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/st,stm32-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_PATH "/soc/timers@40013400/qdec"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_FULL_NAME "qdec"
#define DT_N_S_soc_S_timers_40013400_S_qdec_FULL_NAME_UNQUOTED qdec
#define DT_N_S_soc_S_timers_40013400_S_qdec_FULL_NAME_TOKEN qdec
#define DT_N_S_soc_S_timers_40013400_S_qdec_FULL_NAME_UPPER_TOKEN QDEC

/* Node parent (/soc/timers@40013400) identifier: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_PARENT DT_N_S_soc_S_timers_40013400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40013400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40013400_S_qdec_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_HASH BFDRq_VhlZoMiQzn4wkHhwfPzJOfS8CeuuJpL42mkT8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_ORD 134
#define DT_N_S_soc_S_timers_40013400_S_qdec_ORD_STR_SORTABLE 00134

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_REQUIRES_ORDS \
	131, /* /soc/timers@40013400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_EXISTS 1
#define DT_N_INST_4_st_stm32_qdec DT_N_S_soc_S_timers_40013400_S_qdec

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_REG_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40013400_S_qdec_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_COMPAT_MATCHES_st_stm32_qdec 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40013400_S_qdec_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_COMPAT_MODEL_IDX_0 "stm32-qdec"
#define DT_N_S_soc_S_timers_40013400_S_qdec_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_encoder_mode 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_encoder_mode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_encoder_mode_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_encoder_mode_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_encoder_mode_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_polarity_inverted 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_polarity_inverted_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_filter_level 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_filter_level_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_filter_level_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_filter_level_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_filter_level_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_st_input_filter_level_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status "disabled"
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_qdec, status, 0)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_qdec, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_LEN 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible {"st,stm32-qdec"}
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_IDX_0 "st,stm32-qdec"
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qdec
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_IDX_0_STRING_TOKEN st_stm32_qdec
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QDEC
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40013400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40013400_S_qdec, compatible, 0)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40013400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40013400_S_qdec, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40013400_S_qdec_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014000
 *
 * Node identifier: DT_N_S_soc_S_timers_40014000
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014000_PATH "/soc/timers@40014000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014000_FULL_NAME "timers@40014000"
#define DT_N_S_soc_S_timers_40014000_FULL_NAME_UNQUOTED timers@40014000
#define DT_N_S_soc_S_timers_40014000_FULL_NAME_TOKEN timers_40014000
#define DT_N_S_soc_S_timers_40014000_FULL_NAME_UPPER_TOKEN TIMERS_40014000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40014000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014000_CHILD_IDX 32

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014000_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40014000_FOREACH_NODELABEL(fn) fn(timers15)
#define DT_N_S_soc_S_timers_40014000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers15, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014000_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40014000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000_S_counter)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014000_HASH lq5p3vgPpp0Pc1e97jH3shzpysrGZocBMMy1grfenUs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014000_ORD 135
#define DT_N_S_soc_S_timers_40014000_ORD_STR_SORTABLE 00135

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014000_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014000_SUPPORTS_ORDS \
	136, /* /soc/timers@40014000/counter */ \
	137, /* /soc/timers@40014000/pwm */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014000_EXISTS 1
#define DT_N_INST_7_st_stm32_timers DT_N_S_soc_S_timers_40014000
#define DT_N_NODELABEL_timers15     DT_N_S_soc_S_timers_40014000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014000_REG_NUM 1
#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_ADDRESS 1073823744 /* 0x40014000 */
#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40014000, 0)
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, 0)
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014000_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40014000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40014000_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40014000_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40014000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40014000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014000_P_reg {1073823744 /* 0x40014000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0 1073823744
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40014000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits 65536
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bus 10
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1)
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1)
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014000, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40014000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id 2064
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014000, resets, 0, id)
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, resets, 0, id)
#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, resets, 0)
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, resets, 0)
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40014000_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_countermode 0
#define DT_N_S_soc_S_timers_40014000_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40014000_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status "disabled"
#define DT_N_S_soc_S_timers_40014000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, status, 0)
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, status, 0)
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40014000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014000_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014000/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40014000_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014000_S_counter_PATH "/soc/timers@40014000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40014000) identifier: */
#define DT_N_S_soc_S_timers_40014000_S_counter_PARENT DT_N_S_soc_S_timers_40014000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014000_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014000_S_counter_HASH HTxmpxrEMdGrjqKzwYEQ3Db8lHf9V4eSc5b5awosPW0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014000_S_counter_ORD 136
#define DT_N_S_soc_S_timers_40014000_S_counter_ORD_STR_SORTABLE 00136

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014000_S_counter_REQUIRES_ORDS \
	135, /* /soc/timers@40014000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014000_S_counter_EXISTS 1
#define DT_N_INST_7_st_stm32_counter DT_N_S_soc_S_timers_40014000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40014000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014000/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40014000_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_PATH "/soc/timers@40014000/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40014000) identifier: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_PARENT DT_N_S_soc_S_timers_40014000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014000_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_HASH kSLo0yu1rvkKjWd1KPNaOZTkLqT1fXRh8ItGZQcov88

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD 137
#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD_STR_SORTABLE 00137

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_REQUIRES_ORDS \
	135, /* /soc/timers@40014000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_EXISTS 1
#define DT_N_INST_5_st_stm32_pwm DT_N_S_soc_S_timers_40014000_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014000_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40014000_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014400
 *
 * Node identifier: DT_N_S_soc_S_timers_40014400
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014400_PATH "/soc/timers@40014400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014400_FULL_NAME "timers@40014400"
#define DT_N_S_soc_S_timers_40014400_FULL_NAME_UNQUOTED timers@40014400
#define DT_N_S_soc_S_timers_40014400_FULL_NAME_TOKEN timers_40014400
#define DT_N_S_soc_S_timers_40014400_FULL_NAME_UPPER_TOKEN TIMERS_40014400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40014400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014400_CHILD_IDX 33

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014400_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40014400_FOREACH_NODELABEL(fn) fn(timers16)
#define DT_N_S_soc_S_timers_40014400_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers16, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014400_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40014400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400_S_counter)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014400_HASH LhbzUUvofdpe9RJBdWKw1tw8MqV4XObGHJe29iNM0Lc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014400_ORD 138
#define DT_N_S_soc_S_timers_40014400_ORD_STR_SORTABLE 00138

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014400_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014400_SUPPORTS_ORDS \
	139, /* /soc/timers@40014400/counter */ \
	140, /* /soc/timers@40014400/pwm */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014400_EXISTS 1
#define DT_N_INST_8_st_stm32_timers DT_N_S_soc_S_timers_40014400
#define DT_N_NODELABEL_timers16     DT_N_S_soc_S_timers_40014400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014400_REG_NUM 1
#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_ADDRESS 1073824768 /* 0x40014400 */
#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40014400, 0)
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, 0)
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014400_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40014400_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40014400_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40014400_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40014400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40014400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014400_P_reg {1073824768 /* 0x40014400 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0 1073824768
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40014400_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits 131072
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bus 10
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1)
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1)
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014400, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40014400_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id 2065
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014400, resets, 0, id)
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, resets, 0, id)
#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, resets, 0)
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, resets, 0)
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40014400_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_countermode 0
#define DT_N_S_soc_S_timers_40014400_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40014400_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status "disabled"
#define DT_N_S_soc_S_timers_40014400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, status, 0)
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, status, 0)
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupts {25 /* 0x19 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40014400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014400_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014400/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40014400_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014400_S_counter_PATH "/soc/timers@40014400/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40014400) identifier: */
#define DT_N_S_soc_S_timers_40014400_S_counter_PARENT DT_N_S_soc_S_timers_40014400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014400_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014400_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014400_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014400_S_counter_HASH p37X7wit0iPn8X9v8y4Gj2t07AN6oeaaeHeLb6OojSE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014400_S_counter_ORD 139
#define DT_N_S_soc_S_timers_40014400_S_counter_ORD_STR_SORTABLE 00139

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014400_S_counter_REQUIRES_ORDS \
	138, /* /soc/timers@40014400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014400_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014400_S_counter_EXISTS 1
#define DT_N_INST_8_st_stm32_counter DT_N_S_soc_S_timers_40014400_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014400_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014400_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40014400_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014400_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014400/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40014400_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_PATH "/soc/timers@40014400/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40014400) identifier: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_PARENT DT_N_S_soc_S_timers_40014400

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014400_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_HASH qSncIfFrKmBeFCfySGntGi5dvRM62NXtfq0Z60Th_Tw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD 140
#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD_STR_SORTABLE 00140

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_REQUIRES_ORDS \
	138, /* /soc/timers@40014400 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_EXISTS 1
#define DT_N_INST_6_st_stm32_pwm DT_N_S_soc_S_timers_40014400_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014400_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40014400_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014800
 *
 * Node identifier: DT_N_S_soc_S_timers_40014800
 *
 * Binding (compatible = st,stm32-timers):
 *   $ZEPHYR_BASE/dts/bindings/timer/st,stm32-timers.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014800_PATH "/soc/timers@40014800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014800_FULL_NAME "timers@40014800"
#define DT_N_S_soc_S_timers_40014800_FULL_NAME_UNQUOTED timers@40014800
#define DT_N_S_soc_S_timers_40014800_FULL_NAME_TOKEN timers_40014800
#define DT_N_S_soc_S_timers_40014800_FULL_NAME_UPPER_TOKEN TIMERS_40014800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timers_40014800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014800_CHILD_IDX 34

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014800_NODELABEL_NUM 1
#define DT_N_S_soc_S_timers_40014800_FOREACH_NODELABEL(fn) fn(timers17)
#define DT_N_S_soc_S_timers_40014800_FOREACH_NODELABEL_VARGS(fn, ...) fn(timers17, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014800_CHILD_NUM 2
#define DT_N_S_soc_S_timers_40014800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800_S_counter)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014800_HASH HFfK32JNDgTzZmhucfswXs63t4LSBAvBFi__WAnpexw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014800_ORD 141
#define DT_N_S_soc_S_timers_40014800_ORD_STR_SORTABLE 00141

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014800_REQUIRES_ORDS \
	4, /* /soc */ \
	5, /* /soc/interrupt-controller@e000e100 */ \
	9, /* /soc/rcc@40021000 */ \
	46, /* /soc/rcc@40021000/reset-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014800_SUPPORTS_ORDS \
	142, /* /soc/timers@40014800/counter */ \
	143, /* /soc/timers@40014800/pwm */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014800_EXISTS 1
#define DT_N_INST_9_st_stm32_timers DT_N_S_soc_S_timers_40014800
#define DT_N_NODELABEL_timers17     DT_N_S_soc_S_timers_40014800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014800_REG_NUM 1
#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_ADDRESS 1073825792 /* 0x40014800 */
#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG(fn) fn(DT_N_S_soc_S_timers_40014800, 0)
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, 0)
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014800_IRQ_NUM 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_irq 26
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timers_40014800_IRQ_LEVEL 1
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_irq DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_irq
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_priority DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_VAL_priority
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_IRQ_NAME_global_CONTROLLER DT_N_S_soc_S_timers_40014800_IRQ_IDX_0_CONTROLLER
#define DT_N_S_soc_S_timers_40014800_COMPAT_MATCHES_st_stm32_timers 1
#define DT_N_S_soc_S_timers_40014800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_COMPAT_MODEL_IDX_0 "stm32-timers"
#define DT_N_S_soc_S_timers_40014800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014800_P_reg {1073825792 /* 0x40014800 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0 1073825792
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1 1024
#define DT_N_S_soc_S_timers_40014800_P_reg_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus 96
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits 262144
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bus) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 0, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_40021000
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bus 10
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bus_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bits 255
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_VAL_bits_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bus) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bus) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, bits)
#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_1_NUM_CELLS 2
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1)
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1)
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_timers_40014800, clocks, 1, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_clocks_LEN 2
#define DT_N_S_soc_S_timers_40014800_P_clocks_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_40021000_S_reset_controller
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id 2066
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_timers_40014800, resets, 0, id)
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, resets, 0, id)
#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, resets, 0)
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, resets, 0)
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_resets_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_resets_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_prescaler 0
#define DT_N_S_soc_S_timers_40014800_P_st_prescaler_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_countermode 0
#define DT_N_S_soc_S_timers_40014800_P_st_countermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_deadtime 0
#define DT_N_S_soc_S_timers_40014800_P_st_deadtime_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode "RESET"
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_STRING_TOKEN RESET
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0 "RESET"
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_IDX_0_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_ENUM_VAL_reset_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, st_mastermode, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_st_mastermode_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status "disabled"
#define DT_N_S_soc_S_timers_40014800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, status, 0)
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, status, 0)
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_compatible {"st,stm32-timers"}
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0 "st,stm32-timers"
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers
#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupts {26 /* 0x1a */, 0 /* 0x0 */}
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0 26
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_timers_40014800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names {"global"}
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0 "global"
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_UNQUOTED global
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_TOKEN global
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_LEN 1
#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014800_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014800/counter
 *
 * Node identifier: DT_N_S_soc_S_timers_40014800_S_counter
 *
 * Binding (compatible = st,stm32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/st,stm32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014800_S_counter_PATH "/soc/timers@40014800/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/timers@40014800) identifier: */
#define DT_N_S_soc_S_timers_40014800_S_counter_PARENT DT_N_S_soc_S_timers_40014800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014800_S_counter_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014800_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014800_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014800_S_counter_HASH S6y2pTOmJHjQSdFjECAm7CIldgBp6UkB1xRx45LXe9E

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014800_S_counter_ORD 142
#define DT_N_S_soc_S_timers_40014800_S_counter_ORD_STR_SORTABLE 00142

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014800_S_counter_REQUIRES_ORDS \
	141, /* /soc/timers@40014800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014800_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014800_S_counter_EXISTS 1
#define DT_N_INST_9_st_stm32_counter DT_N_S_soc_S_timers_40014800_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014800_S_counter_REG_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014800_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_MATCHES_st_stm32_counter 1
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_COMPAT_MODEL_IDX_0 "stm32-counter"
#define DT_N_S_soc_S_timers_40014800_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014800_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status "disabled"
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible {"st,stm32-counter"}
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0 "st,stm32-counter"
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/timers@40014800/pwm
 *
 * Node identifier: DT_N_S_soc_S_timers_40014800_S_pwm
 *
 * Binding (compatible = st,stm32-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/st,stm32-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_PATH "/soc/timers@40014800/pwm"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME "pwm"
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_UNQUOTED pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_TOKEN pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_UPPER_TOKEN PWM

/* Node parent (/soc/timers@40014800) identifier: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_PARENT DT_N_S_soc_S_timers_40014800

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_NODELABEL_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timers_40014800_S_pwm_CHILD_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_HASH pP_vpmBmH6Uc99dxi1iL0vcGxl00Y6rTzAdbQLvVodY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD 143
#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD_STR_SORTABLE 00143

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_REQUIRES_ORDS \
	141, /* /soc/timers@40014800 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_EXISTS 1
#define DT_N_INST_7_st_stm32_pwm DT_N_S_soc_S_timers_40014800_S_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_REG_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_RANGES_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timers_40014800_S_pwm_IRQ_NUM 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_IRQ_LEVEL 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_MATCHES_st_stm32_pwm 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_VENDOR_IDX_0 "STMicroelectronics"
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_COMPAT_MODEL_IDX_0 "stm32-pwm"
#define DT_N_S_soc_S_timers_40014800_S_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status "disabled"
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible {"st,stm32-pwm"}
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm"
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_LEN 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_dma_coherent 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_dma_coherent_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_crc                     DT_N_S_soc_S_crc_40023000
#define DT_CHOSEN_zephyr_crc_EXISTS              1
#define DT_CHOSEN_zephyr_entropy                 DT_N_S_soc_S_rng_50060800
#define DT_CHOSEN_zephyr_entropy_EXISTS          1
#define DT_CHOSEN_zephyr_flash_controller        DT_N_S_soc_S_flash_controller_40022000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS 1
#define DT_CHOSEN_zephyr_console                 DT_N_S_soc_S_serial_40008000
#define DT_CHOSEN_zephyr_console_EXISTS          1
#define DT_CHOSEN_zephyr_shell_uart              DT_N_S_soc_S_serial_40008000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS       1
#define DT_CHOSEN_zephyr_sram                    DT_N_S_memory_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS             1
#define DT_CHOSEN_zephyr_flash                   DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_CHOSEN_zephyr_flash_EXISTS            1
#define DT_CHOSEN_zephyr_code_partition          DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_adc_50000000) fn(DT_N_S_soc_S_adc_50000100) fn(DT_N_S_soc_S_dac_50000800) fn(DT_N_S_soc_S_dac_50001000) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca) fn(DT_N_S_soc_S_rcc_40021000) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_40010400) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4) fn(DT_N_S_soc_S_serial_40013800) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40008000) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_watchdog_40002c00) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40007800) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_can_40006400) fn(DT_N_S_soc_S_timers_40007c00) fn(DT_N_S_soc_S_timers_40012c00) fn(DT_N_S_soc_S_timers_40012c00_S_pwm) fn(DT_N_S_soc_S_timers_40012c00_S_counter) fn(DT_N_S_soc_S_timers_40012c00_S_qdec) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_qdec) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_qdec) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_qdec) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001000_S_counter) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40001400_S_counter) fn(DT_N_S_soc_S_timers_40013400) fn(DT_N_S_soc_S_timers_40013400_S_pwm) fn(DT_N_S_soc_S_timers_40013400_S_counter) fn(DT_N_S_soc_S_timers_40013400_S_qdec) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_soc_S_usb_40005c00) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_ucpd_4000a000) fn(DT_N_S_soc_S_sai1_40015404) fn(DT_N_S_soc_S_sai1_40015424) fn(DT_N_S_soc_S_opamp1_40010300) fn(DT_N_S_soc_S_opamp2_40010304) fn(DT_N_S_soc_S_opamp3_40010308) fn(DT_N_S_soc_S_comparator_40010200) fn(DT_N_S_soc_S_comparator_40010204) fn(DT_N_S_soc_S_crc_40023000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus_S_power_states_S_state0) fn(DT_N_S_cpus_S_power_states_S_state1) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll) fn(DT_N_S_dietemp) fn(DT_N_S_vref) fn(DT_N_S_vbat) fn(DT_N_S_usbphy) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_connector) fn(DT_N_S_st_morpho_header) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_green_pwm_led) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_dac_50000800) fn(DT_N_S_soc_S_flash_controller_40022000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca) fn(DT_N_S_soc_S_rcc_40021000) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_40010400) fn(DT_N_S_soc_S_pin_controller_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4) fn(DT_N_S_soc_S_serial_40013800) fn(DT_N_S_soc_S_serial_40008000) fn(DT_N_S_soc_S_watchdog_40003000) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_timers_40007c00) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_rtc_40002800) fn(DT_N_S_soc_S_rng_50060800) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus_S_power_states_S_state0) fn(DT_N_S_cpus_S_power_states_S_state1) fn(DT_N_S_memory_20000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll) fn(DT_N_S_usbphy) fn(DT_N_S_connector) fn(DT_N_S_st_morpho_header) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_green_pwm_led) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button)
#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_adc_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_50000100, __VA_ARGS__) fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__) fn(DT_N_S_soc_S_dac_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40002c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_40006400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40012c00_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40013400_S_qdec, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_ucpd_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015404, __VA_ARGS__) fn(DT_N_S_soc_S_sai1_40015424, __VA_ARGS__) fn(DT_N_S_soc_S_opamp1_40010300, __VA_ARGS__) fn(DT_N_S_soc_S_opamp2_40010304, __VA_ARGS__) fn(DT_N_S_soc_S_opamp3_40010308, __VA_ARGS__) fn(DT_N_S_soc_S_comparator_40010200, __VA_ARGS__) fn(DT_N_S_soc_S_comparator_40010204, __VA_ARGS__) fn(DT_N_S_soc_S_crc_40023000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_usbphy, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_st_morpho_header, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_green_pwm_led, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)
#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal1_a8, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_vrefint_aa, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout_S_ts_cal2_ca, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_miso_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_miso_pb14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_miso_pc11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_mosi_pa7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_mosi_pb15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_mosi_pc12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_nss_pb12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_nss_pa15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi1_sck_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi2_sck_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_spi3_sck_pc10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_tim2_ch1_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_rx_pa3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_rx_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_lpuart1_tx_pa2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_usart1_tx_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__) fn(DT_N_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll, __VA_ARGS__) fn(DT_N_S_usbphy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_st_morpho_header, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_green_pwm_led, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button, __VA_ARGS__)

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0_NVM_DEVICE DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_mcuboot DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0
#define DT_COMPAT_zephyr_mapped_partition_LABEL_mcuboot_EXISTS 1

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800_NVM_DEVICE DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_0 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_0_EXISTS 1

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800_NVM_DEVICE DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_1 DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800
#define DT_COMPAT_zephyr_mapped_partition_LABEL_image_1_EXISTS 1

/* parent NVM identifier: */
#define DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000_NVM_DEVICE DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_storage DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000
#define DT_COMPAT_zephyr_mapped_partition_LABEL_storage_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_st_stm32g431rb_nucleo 1
#define DT_COMPAT_HAS_OKAY_st_stm32g431 1
#define DT_COMPAT_HAS_OKAY_st_stm32g4 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v7m_nvic 1
#define DT_COMPAT_HAS_OKAY_arm_armv7m_systick 1
#define DT_COMPAT_HAS_OKAY_st_stm32_dac 1
#define DT_COMPAT_HAS_OKAY_st_stm32_flash_controller 1
#define DT_COMPAT_HAS_OKAY_st_stm32g4_flash_controller 1
#define DT_COMPAT_HAS_OKAY_st_stm32_nv_flash 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_zephyr_mapped_partition 1
#define DT_COMPAT_HAS_OKAY_st_stm32_nvm_otp 1
#define DT_COMPAT_HAS_OKAY_fixed_layout 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rcc 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rcc_rctl 1
#define DT_COMPAT_HAS_OKAY_st_stm32_exti 1
#define DT_COMPAT_HAS_OKAY_st_stm32_pinctrl 1
#define DT_COMPAT_HAS_OKAY_st_stm32_gpio 1
#define DT_COMPAT_HAS_OKAY_st_stm32_usart 1
#define DT_COMPAT_HAS_OKAY_st_stm32_uart 1
#define DT_COMPAT_HAS_OKAY_st_stm32_lpuart 1
#define DT_COMPAT_HAS_OKAY_st_stm32_watchdog 1
#define DT_COMPAT_HAS_OKAY_st_stm32_i2c_v2 1
#define DT_COMPAT_HAS_OKAY_st_stm32_spi_fifo 1
#define DT_COMPAT_HAS_OKAY_st_stm32_spi 1
#define DT_COMPAT_HAS_OKAY_st_stm32_lptim 1
#define DT_COMPAT_HAS_OKAY_st_stm32_timers 1
#define DT_COMPAT_HAS_OKAY_st_stm32_pwm 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rtc 1
#define DT_COMPAT_HAS_OKAY_st_stm32_rng 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m4f 1
#define DT_COMPAT_HAS_OKAY_zephyr_power_state 1
#define DT_COMPAT_HAS_OKAY_zephyr_memory_region 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_st_stm32_hse_clock 1
#define DT_COMPAT_HAS_OKAY_fixed_clock 1
#define DT_COMPAT_HAS_OKAY_st_stm32_lse_clock 1
#define DT_COMPAT_HAS_OKAY_st_stm32g4_pll_clock 1
#define DT_COMPAT_HAS_OKAY_usb_nop_xceiv 1
#define DT_COMPAT_HAS_OKAY_arduino_header_r3 1
#define DT_COMPAT_HAS_OKAY_st_morpho_header 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_pwm_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_st_stm32g431rb_nucleo_NUM_OKAY 1
#define DT_N_INST_st_stm32g431_NUM_OKAY 1
#define DT_N_INST_st_stm32g4_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v7m_nvic_NUM_OKAY 1
#define DT_N_INST_arm_armv7m_systick_NUM_OKAY 1
#define DT_N_INST_st_stm32_dac_NUM_OKAY 1
#define DT_N_INST_st_stm32_flash_controller_NUM_OKAY 1
#define DT_N_INST_st_stm32g4_flash_controller_NUM_OKAY 1
#define DT_N_INST_st_stm32_nv_flash_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_zephyr_mapped_partition_NUM_OKAY 4
#define DT_N_INST_st_stm32_nvm_otp_NUM_OKAY 1
#define DT_N_INST_fixed_layout_NUM_OKAY 1
#define DT_N_INST_st_stm32_rcc_NUM_OKAY 1
#define DT_N_INST_st_stm32_rcc_rctl_NUM_OKAY 1
#define DT_N_INST_st_stm32_exti_NUM_OKAY 1
#define DT_N_INST_st_stm32_pinctrl_NUM_OKAY 1
#define DT_N_INST_st_stm32_gpio_NUM_OKAY 7
#define DT_N_INST_st_stm32_usart_NUM_OKAY 1
#define DT_N_INST_st_stm32_uart_NUM_OKAY 2
#define DT_N_INST_st_stm32_lpuart_NUM_OKAY 1
#define DT_N_INST_st_stm32_watchdog_NUM_OKAY 1
#define DT_N_INST_st_stm32_i2c_v2_NUM_OKAY 1
#define DT_N_INST_st_stm32_spi_fifo_NUM_OKAY 3
#define DT_N_INST_st_stm32_spi_NUM_OKAY 3
#define DT_N_INST_st_stm32_lptim_NUM_OKAY 1
#define DT_N_INST_st_stm32_timers_NUM_OKAY 1
#define DT_N_INST_st_stm32_pwm_NUM_OKAY 1
#define DT_N_INST_st_stm32_rtc_NUM_OKAY 1
#define DT_N_INST_st_stm32_rng_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m4f_NUM_OKAY 1
#define DT_N_INST_zephyr_power_state_NUM_OKAY 2
#define DT_N_INST_zephyr_memory_region_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_st_stm32_hse_clock_NUM_OKAY 1
#define DT_N_INST_fixed_clock_NUM_OKAY 2
#define DT_N_INST_st_stm32_lse_clock_NUM_OKAY 1
#define DT_N_INST_st_stm32g4_pll_clock_NUM_OKAY 1
#define DT_N_INST_usb_nop_xceiv_NUM_OKAY 1
#define DT_N_INST_arduino_header_r3_NUM_OKAY 1
#define DT_N_INST_st_morpho_header_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_pwm_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_FOREACH_OKAY_st_stm32g431rb_nucleo(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_st_stm32g431rb_nucleo(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32g431rb_nucleo(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32g431rb_nucleo(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32g431(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_st_stm32g431(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32g431(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32g431(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32g4(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_st_stm32g4(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32g4(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32g4(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_v7m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100)
#define DT_FOREACH_OKAY_VARGS_arm_v7m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_v7m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_v7m_nvic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv7m_systick(fn) fn(DT_N_S_soc_S_timer_e000e010)
#define DT_FOREACH_OKAY_VARGS_arm_armv7m_systick(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv7m_systick(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv7m_systick(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_dac(fn) fn(DT_N_S_soc_S_dac_50000800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_dac(fn, ...) fn(DT_N_S_soc_S_dac_50000800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_dac(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_dac(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_flash_controller(fn) fn(DT_N_S_soc_S_flash_controller_40022000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_flash_controller(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32g4_flash_controller(fn) fn(DT_N_S_soc_S_flash_controller_40022000)
#define DT_FOREACH_OKAY_VARGS_st_stm32g4_flash_controller(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32g4_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32g4_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_mapped_partition(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000)
#define DT_FOREACH_OKAY_VARGS_zephyr_mapped_partition(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_8800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_14800, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_8000000_S_partitions_S_partition_1f000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_mapped_partition(fn) fn(0) fn(1) fn(2) fn(3)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_mapped_partition(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_nvm_otp(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500)
#define DT_FOREACH_OKAY_VARGS_st_stm32_nvm_otp(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_nvm_otp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_nvm_otp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_layout(fn) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout)
#define DT_FOREACH_OKAY_VARGS_fixed_layout(fn, ...) fn(DT_N_S_soc_S_flash_controller_40022000_S_flash_1fff7500_S_nvmem_layout, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_layout(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_layout(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rcc(fn) fn(DT_N_S_soc_S_rcc_40021000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rcc(fn, ...) fn(DT_N_S_soc_S_rcc_40021000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rcc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rcc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rcc_rctl(fn) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rcc_rctl(fn, ...) fn(DT_N_S_soc_S_rcc_40021000_S_reset_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rcc_rctl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rcc_rctl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_exti(fn) fn(DT_N_S_soc_S_interrupt_controller_40010400)
#define DT_FOREACH_OKAY_VARGS_st_stm32_exti(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_40010400, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_exti(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_exti(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_pinctrl(fn) fn(DT_N_S_soc_S_pin_controller_48000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_pinctrl(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_gpio(fn) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_gpio(fn, ...) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48000c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_48000000_S_gpio_48001800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_gpio(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5) fn(6)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__) fn(6, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_usart(fn) fn(DT_N_S_soc_S_serial_40013800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_usart(fn, ...) fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_usart(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_usart(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_uart(fn) fn(DT_N_S_soc_S_serial_40013800) fn(DT_N_S_soc_S_serial_40008000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_uart(fn, ...) fn(DT_N_S_soc_S_serial_40013800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_uart(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_uart(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_lpuart(fn) fn(DT_N_S_soc_S_serial_40008000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_lpuart(fn, ...) fn(DT_N_S_soc_S_serial_40008000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_lpuart(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_lpuart(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_watchdog(fn) fn(DT_N_S_soc_S_watchdog_40003000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_watchdog(fn, ...) fn(DT_N_S_soc_S_watchdog_40003000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_watchdog(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_watchdog(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_i2c_v2(fn) fn(DT_N_S_soc_S_i2c_40005400)
#define DT_FOREACH_OKAY_VARGS_st_stm32_i2c_v2(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_i2c_v2(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_i2c_v2(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_spi_fifo(fn) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00)
#define DT_FOREACH_OKAY_VARGS_st_stm32_spi_fifo(fn, ...) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_spi_fifo(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_spi_fifo(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_spi(fn) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00)
#define DT_FOREACH_OKAY_VARGS_st_stm32_spi(fn, ...) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_spi(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_spi(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_lptim(fn) fn(DT_N_S_soc_S_timers_40007c00)
#define DT_FOREACH_OKAY_VARGS_st_stm32_lptim(fn, ...) fn(DT_N_S_soc_S_timers_40007c00, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_lptim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_lptim(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_timers(fn) fn(DT_N_S_soc_S_timers_40000000)
#define DT_FOREACH_OKAY_VARGS_st_stm32_timers(fn, ...) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_timers(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_timers(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_pwm(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm)
#define DT_FOREACH_OKAY_VARGS_st_stm32_pwm(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_pwm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_pwm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rtc(fn) fn(DT_N_S_soc_S_rtc_40002800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rtc(fn, ...) fn(DT_N_S_soc_S_rtc_40002800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rtc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rtc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_rng(fn) fn(DT_N_S_soc_S_rng_50060800)
#define DT_FOREACH_OKAY_VARGS_st_stm32_rng(fn, ...) fn(DT_N_S_soc_S_rng_50060800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_rng(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_rng(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cortex_m4f(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m4f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cortex_m4f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m4f(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_power_state(fn) fn(DT_N_S_cpus_S_power_states_S_state0) fn(DT_N_S_cpus_S_power_states_S_state1)
#define DT_FOREACH_OKAY_VARGS_zephyr_power_state(fn, ...) fn(DT_N_S_cpus_S_power_states_S_state0, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_state1, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_power_state(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_power_state(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_memory_region(fn) fn(DT_N_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_zephyr_memory_region(fn, ...) fn(DT_N_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_memory_region(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_memory_region(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_hse_clock(fn) fn(DT_N_S_clocks_S_clk_hse)
#define DT_FOREACH_OKAY_VARGS_st_stm32_hse_clock(fn, ...) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_hse_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_hse_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_clock(fn) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lsi)
#define DT_FOREACH_OKAY_VARGS_fixed_clock(fn, ...) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_clock(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_clock(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32_lse_clock(fn) fn(DT_N_S_clocks_S_clk_lse)
#define DT_FOREACH_OKAY_VARGS_st_stm32_lse_clock(fn, ...) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32_lse_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32_lse_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_stm32g4_pll_clock(fn) fn(DT_N_S_clocks_S_pll)
#define DT_FOREACH_OKAY_VARGS_st_stm32g4_pll_clock(fn, ...) fn(DT_N_S_clocks_S_pll, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_stm32g4_pll_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_stm32g4_pll_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_usb_nop_xceiv(fn) fn(DT_N_S_usbphy)
#define DT_FOREACH_OKAY_VARGS_usb_nop_xceiv(fn, ...) fn(DT_N_S_usbphy, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_usb_nop_xceiv(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_usb_nop_xceiv(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arduino_header_r3(fn) fn(DT_N_S_connector)
#define DT_FOREACH_OKAY_VARGS_arduino_header_r3(fn, ...) fn(DT_N_S_connector, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arduino_header_r3(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arduino_header_r3(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_st_morpho_header(fn) fn(DT_N_S_st_morpho_header)
#define DT_FOREACH_OKAY_VARGS_st_morpho_header(fn, ...) fn(DT_N_S_st_morpho_header, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_st_morpho_header(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_st_morpho_header(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_pwmleds)
#define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_pwmleds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_gpio_keys)
#define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_gpio_keys, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
